ADSP-2184NKCA-320 データシートの表示（PDF） - Analog Devices

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ADSP-2184NKCA-320

DSP Microcomputer

Analog Devices 

ADSP-218xN Series

SYSTEM CONTROL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0X3FFF)

RESERVED

SET TO 0

SPORT0 ENABLE

0 = DISABLE

1 = ENABLE

SPORT1 ENABLE

0 = DISABLE

1 = ENABLE

RESERVED, ALWAYS

SET TO 0

PWAIT

PROGRAM MEMORY

WAIT STATES

DI SA BL E BMS

0 = EN AB LE BMS

1 = DISABL E BMS

SPORT1 CONFIGURE

0 = FI, FO, IRQ0, IRQ1, SC LK

1 = SPORT1

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS

SHOULD ALWAYS BE WRITTEN WITH ZEROS.

Figure 11. System Control Register

Byte Memory Select

The ADSP-218xN’s BMS disable feature combined with

the CMS pin allows use of multiple memories in the byte

memory space. For example, an EPROM could be attached

to the BMS select, and a flash memory could be connected

to CMS. Because at reset BMS is enabled, the EPROM

would be used for booting. After booting, software could

disable BMS and set the CMS signal to respond to BMS,

enabling the flash memory.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide,

external memory space used to store programs and data.

Byte memory is accessed using the BDMA feature. The byte

memory space consists of 256 pages, each of which is

16K ؋ 8 bits.

The byte memory space on the ADSP-218xN series sup-

ports read and write operations as well as four different data

formats. The byte memory uses data bits 15–8 for data. The

byte memory uses data bits 23–16 and address bits 13–0

to create a 22-bit address. This allows up to a 4 meg ؋ 8

(32 megabit) ROM or RAM to be used without glue logic.

All byte memory accesses are timed by the BMWAIT reg-

ister and the wait state mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller (Figure 12) allows

loading and storing of program instructions and data using

the byte memory space. The BDMA circuit is able to access

the byte memory space while the processor is operating

normally and steals only one DSP cycle per 8-, 16-, or 24-

bit word transferred.

BDMA CONTROL

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM (0x3FE3)

BMPAGE

BDMA

OVERLAY

BITS

(SEE TABLE 12)

BTYPE

BDIR

0 = LOAD FROM BM

1 = STORE TO BM

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Figure 12. BDMA Control Register

The BDMA circuit supports four different data formats that

are selected by the BTYPE register field. The appropriate

number of 8-bit accesses are done from the byte memory

space to build the word size selected. Table 11 shows the

data formats supported by the BDMA circuit.

Table 11. Data Formats

BTYPE

00

01

10

11

Internal

Memory Space

Program

Memory

Data Memory

Data Memory

Data Memory

Word Size Alignment

24

Full Word

16

Full Word

8

MSBs

8

LSBs

Unused bits in the 8-bit data memory formats are filled with

0s. The BIAD register field is used to specify the starting

address for the on-chip memory involved with the transfer.

The 14-bit BEAD register specifies the starting address for

the external byte memory space. The 8-bit BMPAGE reg-

ister specifies the starting page for the external byte memory

space. The BDIR register field selects the direction of the

transfer. Finally, the 14-bit BWCOUNT register specifies

the number of DSP words to transfer and initiates the

BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequen-

tial addressing. A BDMA interrupt is generated on the com-

pletion of the number of transfers specified by the

BWCOUNT register.

The BWCOUNT register is updated after each transfer so

it can be used to check the status of the transfers. When

it reaches zero, the transfers have finished and a BDMA

interrupt is generated. The BMPAGE and BEAD registers

must not be accessed by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always

be on-chip program or data memory.

When the BWCOUNT register is written with a nonzero

value the BDMA circuit starts executing byte memory

accesses with wait states set by BMWAIT. These accesses

continue until the count reaches zero. When enough access-

es have occurred to create a destination word, it is trans-

ferred to or from on-chip memory. The transfer takes one

–16–

REV. 0

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