ADSP-2189NKCA-320 データシートの表示（PDF） - Analog Devices

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ADSP-2189NKCA-320

DSP Microcomputer

Analog Devices 

ADSP-218xN Series

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The

ADSP-218xN series has up to 48K words of Program

Memory RAM on chip, and the capability of accessing up

to two 8K external memory overlay spaces, using the exter-

nal data bus.

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single exter-

nal address line (A0). External program execution is not

available in host mode due to a restricted data bus that is

only 16 bits wide.

Table 8. PMOVLAY Bits

Processor

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

All Processors

PMOVLAY

No Internal

Overlay Region

0

No Internal

Overlay Region

0, 4, 5

0, 4, 5, 6, 7

0, 4, 5

1

All Processors 2

Memory

Not Applicable

A13

Not Applicable

Internal Overlay

Not Applicable

Not Applicable

Not Applicable

Internal Overlay

Internal Overlay

Internal Overlay

External Overlay 1

Not Applicable

Not Applicable

Not Applicable

0

External Overlay 2 1

A12 – 0

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

13 LSBs of Address Between 0x2000 and

0x3FFF

13 LSBs of Address Between 0x2000 and

0x3FFF

Data Memory

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-

mapped control registers. The ADSP-218xN series has up

to 56K words of Data Memory RAM on-chip. Part of this

space is used by 32 memory-mapped registers. Support also

exists for up to two 8K external memory overlay spaces

through the external data bus. All internal accesses com-

plete in one cycle. Accesses to external memory are timed

using the wait states specified by the DWAIT register and

the wait state mode bit.

Data Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single exter-

nal address line (A0).

Table 9. DMOVLAY Bits

Processor

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

All Processors

DMOVLAY

No Internal Overlay

Region

0

No Internal Overlay

Region

0, 4, 5

0, 4, 5, 6, 7, 8

0, 4, 5, 6, 7

1

All Processors 2

Memory

Not Applicable

Internal Overlay

Not Applicable

Internal Overlay

Internal Overlay

Internal Overlay

External Overlay 1

External Overlay 2

A13

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

0

1

A12 – 0

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

Not Applicable

13 LSBs of Address

Between 0x0000

and 0x1FFF

13 LSBs of Address

Between 0x0000

and 0x1FFF

–14–

REV. 0

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