ADSP-2188MKCA-300 データシートの表示（PDF） - Analog Devices

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ADSP-2188MKCA-300

DSP Microcomputer

Analog Devices 

ADSP-2188M

DATA ADDRESS

GENERATORS

DAG1 DAG2

PROGRAM

SEQUENCER

POWER-DOWN

CONTROL

MEMORY

PROGRAM

MEMORY

48K ؋ 24 BIT

DATA

MEMORY

56K ؋ 16 BIT

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

PROGRAMMABLE

I/O

AND

FLAGS

ARITHMETIC UNITS

ALU

MAC SHIFTER

SERIAL PORTS

SPORT0 SPORT1

TIMER

ADSP-2100 BASE

ARCHITECTURE

Figure 1. Functional Block Diagram

FULL MEMORY MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

OR

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

ARCHITECTURE OVERVIEW

The ADSP-2188M instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single

processor cycle. The ADSP-2188M assembly language uses an

algebraic syntax for ease of coding and readability. A compre-

hensive set of development tools supports program development.

Figure 1 is an overall block diagram of the ADSP-2188M. The

processor contains three independent computational units:

the ALU, the multiplier/accumulator (MAC), and the shifter.

The computational units process 16-bit data directly and have

provisions to support multiprecision computations. The ALU

performs a standard set of arithmetic and logic operations;

division primitives are also supported. The MAC performs

single-cycle multiply, multiply/add, and multiply/subtract opera-

tions with 40 bits of accumulation. The shifter performs logical

and arithmetic shifts, normalization, denormalization, and

derive exponent operations.

The shifter can be used to efficiently implement numeric

format control, including multiword and block floating-point

representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these computa-

tional units. The sequencer supports conditional jumps, subroutine

calls, and returns in a single cycle. With internal loop counters

and loop stacks, the ADSP-2188M executes looped code with

zero overhead; no explicit jump instructions are required to

maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modified by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

Efficient data transfer is achieved with the use of five

internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

Program memory can store both instructions and data, permit-

ting the ADSP-2188M to fetch two operands in a single cycle,

one from program memory and one from data memory. The

ADSP-2188M can fetch an operand from program memory and

the next instruction in the same cycle.

In lieu of the address and data bus for external memory connec-

tion, the ADSP-2188M may be configured for 16-bit Internal

DMA port (IDMA port) connection to external systems. The

IDMA port is made up of 16 data/address pins and five control

pins. The IDMA port provides transparent, direct access to the

DSPs on-chip program and data RAM.

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

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