ADSP-21469BBCZ-3 データシートの表示（PDF） - Analog Devices
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ADSP-21469BBCZ-3 Datasheet PDF : 76 Pages
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GENERAL DESCRIPTION
The ADSP-21467/ADSP-21469 SHARC® processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x,
ADSP-2137x, and ADSP-2116x DSPs, as well as with first
generation ADSP-2106x SHARC processors in SISD (single-
instruction, single-data) mode. These 32-bit/40-bit floating-
point processors are optimized for high performance audio
applications with their large on-chip SRAM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative digital
applications/peripheral interfaces (DAI/DPI).
Table 1 shows performance benchmarks for the processor, and
Table 2 shows the product’s features.
Table 1. Processor Benchmarks
Speed
Benchmark Algorithm
(at 450 MHz)
1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s
FIR Filter (Per Tap)1
1.11 ns
IIR Filter (Per Biquad)1
4.43 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
10.0 ns
17.78 ns
Divide (y/x)
6.67 ns
Inverse Square Root
10.0 ns
1 Assumes two files in multichannel SIMD mode
Table 2. SHARC Family Features
Feature
Maximum Frequency
RAM
ROM
Audio Decoders in ROM1
DTCP Hardware Accelerator2
Pulse-Width Modulation
S/PDIF
DDR2 Memory Interface
DDR2 Memory Bus Width
Shared DDR2 External Memory
Direct DMA from SPORTs to
External Memory
FIR, IIR, FFT Accelerator
MLB Interface
IDP
Serial Ports
DAI (SRU)/DPI (SRU2)
UART
Link Ports
AMI Interface with 8-Bit Support
ADSP-21467 ADSP-21469
450 MHz
5 Mbits
4 Mbits
N/A
Yes
No
No
Yes
Yes
Yes
16 Bits
Yes
Yes
Yes
Automotive Models Only
Yes
8
20/14 pins
1
2
Yes
ADSP-21467/ADSP-21469
Table 2. SHARC Family Features (Continued)
Feature
ADSP-21467 ADSP-21469
SPI
2
TWI
Yes
SRC Performance
–128 dB
Package
324-Ball CSP_BGA
1 Factory programmed ROM includes: Dolby AC-3 5.1 Decode, Dolby Pro Logic IIx,
Dolby Intelligent Mixer (eMix), Dolby Volume postprocessor, Dolby Headphone
v2, DTS Neo:6 and Decode, DTS 5.1 Decode (96/24), Math Tables/Twiddle
Factors/256 and 512 FFT, and ASRC. Please visit www.analog.com for complete
product information and availability.
2 Contact your local Analog Devices sales office for more information regarding
availability of ADSP-21467/ADSP-21469 processors which support DTCP.
Figure 1 on Page 1 shows the two clock domains that make up
the processor. The core clock domain contains the following
features:
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• One periodic interval timer with pinout
• PM and DM buses capable of supporting 2 × 64-bit data
transfers between memory and the core at every core pro-
cessor cycle
• On-chip SRAM (5 Mbits)
• On-chip mask-programmable ROM (4 Mbits)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
Figure 1 on Page 1 also shows the peripheral clock domain (also
known as the I/O processor) which contains the following
features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and DDR2 controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), an input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, a 2-
wire interface, one UART, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible
signal routing unit (DPI SRU).
Rev. B | Page 3 of 76 | March 2013
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