ADSP-21469(Rev0) データシートの表示（PDF） - Analog Devices
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ADSP-21469 Datasheet PDF : 72 Pages
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GENERAL DESCRIPTION
The ADSP-21469 SHARC® processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices’ Super Har-
vard Architecture. The processor is source code compatible with
the ADSP-2126x, ADSP-2136x, ADSP-2137x, and ADSP-2116x
DSPs, as well as with first generation ADSP-2106x SHARC pro-
cessors in SISD (single-instruction, single-data) mode. The
processor is a 32-bit/40-bit floating point processor optimized
for high performance audio applications with its large on-chip
SRAM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface (DAI).
Table 1 shows performance benchmarks for the ADSP-21469
processor, and Table 2 shows the product’s features.
Table 1. Processor Benchmarks
Benchmark Algorithm
Speed
(at 450 MHz)
1024 Point Complex FFT (Radix 4, with Reversal) 20.44 s
FIR Filter (Per Tap)1
1.11 ns
IIR Filter (Per Biquad)1
4.43 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
10.0 ns
17.78 ns
Divide (y/x)
6.67 ns
Inverse Square Root
10.0 ns
1 Assumes two files in multichannel SIMD mode
Table 2. SHARC Family Features
Feature
Maximum Frequency
RAM
ROM
Audio Decoders in ROM1
DTCP Hardware Accelerator2
Pulse-Width Modulation
S/PDIF
DDR2 Memory Interface
DDR2 Memory Bus Width
Direct DMA from SPORTs to
External Memory
FIR, IIR, FFT Accelerator
MLB Interface
IDP
Serial Ports
DAI (SRU)/DPI (SRU2)
ADSP-21469
450 MHz
5M Bits
N/A
No
No
Yes
Yes
Yes
16 Bits
Yes
Yes
Automotive Models Only
Yes
8
20/14 pins
ADSP-21469
Table 2. SHARC Family Features (Continued)
Feature
ADSP-21469
UART
1
Link Ports
2
AMI Interface with 8-bit Support
Yes
SPI
2
TWI
Yes
SRC Performance
–128 dB
Package
324-ball CSP_BGA
1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx,
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/postprocessor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
complete product information and availability.
2 These products contain the Digital Transmission Content Protection protocol, a
proprietary security protocol. Contact your Analog Devices sales office for more
information.
Figure 1 on Page 1 shows the two clock domains that make up
the ADSP-21469 processors. The core clock domain contains
the following features:
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• One periodic interval timer with pinout
• PM and DM buses capable of supporting 2 × 64-bit data
transfers between memory and the core at every core pro-
cessor cycle
• On-chip SRAM (5M bit)
• On-chip mask-programmable ROM (4M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
Figure 1 on Page 1 also shows the peripheral clock domain (also
known as the I/O processor) which contains the following
features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and DDR2 controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
Rev. 0 | Page 3 of 72 | June 2010
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