ADSP-21161NKCAZ100 データシートの表示（PDF） - Analog Devices
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ADSP-21161NKCAZ100 Datasheet PDF : 60 Pages
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ADSP-21161N
CLOCK RESET
ADSP-21161N #4
ADSP-21161N #3
CLKIN
RESET
ADDR23-0
DATA47-16
3
ID2-0
CONTROL
ADSP-21161N #2
CLKIN
RESET
ADDR23-0
DATA47-16
2
ID2-0
CONTROL
ADSP-21161N #1
BMS
CLKIN
RESET
ADDR23-0
DATA47-16
RD
1
ID2-0
WR
ACK
MS3-0
SBTS
CS
HBR
HBG
REDY
BR6-2
BR1
RAS
CAS
DQM
SDWE
SDCLK1-0
SDCKE
SDA10
ADDR
DATA
CS
BOOT
EPROM
(OPTIONAL)
ADDR
DATA
OE
WE
ACK
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
CS
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
CS
SDRAM
(OPTIONAL)
ADDR
DATA
Figure 5. Shared Memory Multiprocessing System
setup and message registers. DMA setup via a host would allow
it to access any internal memory address via DMA transfers.
Vector interrupt support provides efficient execution of host
commands.
The host processor interface can be used in either multiproces-
sor or single processor SHARC systems. For multiprocessor
systems, host access to the SHARC requires address pins
ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.
It is not enough to tie these pins to ground through a resistor
Rev. C | Page 8 of 60 | January 2013
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