ADN4668 データシートの表示（PDF） - Analog Devices

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ADN4668

3 V LVDS Quad CMOS Differential Line Receiver

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADN4668

RIN1– 1

RIN1+ 2

RIN2+ 3

RIN2– 4

RIN3– 5

RIN3+ 6

RIN4+ 7

RIN4– 8

16 EN

15 ROUT1

ADN4668

TOP VIEW

(Not to Scale)

14 ROUT2

13 VCC

12 GND

11 ROUT3

10 ROUT4

9 EN

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

RIN1−

Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is

more positive than RIN1+, ROUT1 is low.

2

RIN1+

Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1−, ROUT1 is high. When this input

is more negative than RIN1−, ROUT1 is low.

3

RIN2+

Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2−, ROUT2 is high. When this input

is more negative than RIN2−, ROUT2 is low.

4

RIN2−

Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is

more positive than RIN2+, ROUT2 is low.

5

RIN3−

Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is

more positive than RIN3+, ROUT3 is low.

6

RIN3+

Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3−, ROUT3 is high. When this input

is more negative than RIN3−, ROUT3 is low.

7

RIN4+

Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4−, ROUT4 is high. When this input

is more negative than RIN4−, ROUT4 is low.

8

RIN4−

Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is

more positive than RIN4+, ROUT4 is low.

9

EN

Active-Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). When EN is held high, EN enables the

receiver outputs when EN is low or open circuit and puts the receiver outputs into a high impedance state and

powers down the device when EN is high.

10

ROUT4

Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4− is positive, this

output is high. If the differential input voltage is negative, this output is low.

11

ROUT3

Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3− is positive, this

output is high. If the differential input voltage is negative, this output is low.

12

GND

Ground Reference Point for All Circuitry on the Part.

13

VCC

14

ROUT2

Power Supply Input. These parts can be operated from 3.0 V to 3.6 V.

Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2− is positive, this

output is high. If the differential input voltage is negative, this output is low.

15

ROUT1

Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1− is positive, this

output is high. If the differential input voltage is negative, this output is low.

16

EN

Active-High Enable and Power-Down Input (3 V TTL/CMOS). When EN is held low or open circuit, EN enables the

receiver outputs when EN is high and puts the receiver outputs into a high impedance state and powers down

the device when EN is low.

Rev. A | Page 7 of 12

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