ADN4666ARZ データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADN4666ARZ

3V LVDS Quad CMOS Differential Line Driver

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADN4666

RIN1– 1

RIN1+ 2

ROUT1 3

EN 4

ROUT2 5

RIN2+ 6

RIN2– 7

GND 8

16 VCC

ADN4666

TOP VIEW

(Not to Scale)

15 RIN4–

14 RIN4+

13 ROUT4

12 EN

11 ROUT3

10 RIN3+

9 RIN3–

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

RIN1−

Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is

more positive than RIN1+, ROUT1 is low.

2

RIN1+

Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1−, ROUT1 is high. When this input

is more negative than RIN1−, ROUT1 is low.

3

ROUT1

Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1− is positive, this

output is high. If the differential input voltage is negative, this output is low.

4

EN

Active High Enable and Power-Down Input (3 V TTL/CMOS). When EN is low and EN is high, the receiver outputs

are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low and EN is low,

the receiver outputs are enabled. When EN is high and EN is high, the receiver outputs are enabled.

5

ROUT2

Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2− is positive, this

output is high. If the differential input voltage is negative, this output is low.

6

RIN2+

Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2−, ROUT2 is high. When this input

is more negative than RIN2−, ROUT2 is low.

7

RIN2−

Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is

more positive than RIN2+, ROUT2 is low.

8

GND

Ground Reference Point for All Circuitry on the Part.

9

RIN3−

Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is

more positive than RIN3+, ROUT3 is low.

10

RIN3+

Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3−, ROUT3 is high. When this input

is more negative than RIN3−, ROUT3 is low.

11

ROUT3

Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3− is positive, this

output is high. If the differential input voltage is negative, this output is low.

12

EN

Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). ). When EN is low and EN is high, the

receiver outputs are disabled and are in a high impedance state. When EN is high and EN is low or when EN is low

and EN is low, the receiver outputs are enabled. When EN is high and EN is high, the receiver outputs are enabled.

13

ROUT4

Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4− is positive, this

output is high. If the differential input voltage is negative, this output is low.

14

RIN4+

Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4−, ROUT4 is high. When this input

is more negative than RIN4−, ROUT4 is low.

15

RIN4−

Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is

more positive than RIN4+, ROUT4 is low.

16

VCC

Power Supply Input. The ADN4666 can be operated from 3.0 V to 3.6 V.

Rev. 0 | Page 7 of 12

Share Link: