ADM1070 データシートの表示（PDF） - Analog Devices

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ADM1070

–48 V Hot Swap Controller

Analog Devices 

ADM1070

PIN CONFIGURATION

SENSE 1

6 GATE

ADM1070ART

VEE 2

TOP VIEW

5 UV/OV

(Not to Scale)

VIN 3

4 TIMER

Pin No.

1

2

3

4

5

6

Mnemonic

SENSE

VEE

VIN

TIMER

UV/OV

GATE

PIN FUNCTION DESCRIPTION

Function

Connection to External FET Source Voltage. A sense resistor is connected in the supply path

between the SENSE Pin and VEE, and the voltage across this resistor is monitored to detect current

faults. This voltage is fed as an input to the linear current regulator. When it reaches 100 mV for

a specified period, tON, the regulator reduces the gate voltage and drives the FET as a linear pass

device. If current monitoring is not required, this feature can be turned off by shorting the

SENSE Pin and VEE together.

Device Negative Supply Voltage. This pin should be connected to the lower potential of the

power supply.

Shunt Regulated On-Chip Supply, Nominally VEE + 12.3 V. This pin should be current fed

through a dropper resistor that is connected to the higher potential of the power supply inputs.

Allows User Control over Timing Functions by Determining Frequency of Oscillator. Fre-

quency set by connecting external capacitor to VEE. Tying pin directly to VEE causes oscillator to

default to internally set value.

Input Pin for Overvoltage and Undervoltage Detection Circuitry. The voltage appearing on the

UV/OV Pin is proportional to board supply and is determined by external resistors. When the

voltage on UV/OV falls below the undervoltage threshold of 0.86 V, the GATE Pin is driven low.

When the voltage appearing at the UV/OV Pin rises above the overvoltage threshold of 1.97 V,

the GATE Pin is also driven low. If the external resistor ratio of R1/R2 = 40 is used, then this

gives an operating range of –36 V to –77 V.

Output to External FET Gate Drive. Controlled by linear current regulator. The gate is driven

low if an overvoltage or undervoltage fault occurs or if a current fault lasts for longer than the

time, tON. When in linear regulation, the GATE Pin voltage is controlled as part of the servo loop.

No external compensation is required. When the FET is fully enhanced and the load capacitance

has been charged, the GATE Pin reaches a high level of typically 12 V.

–4–

REV. 0

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