ADL5321-EVALZ(Rev0) データシートの表示（PDF） - Analog Devices
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ADL5321-EVALZ Datasheet PDF : 16 Pages
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ADL5321
BASIC LAYOUT CONNECTIONS
The basic connections for operating the ADL5321 are shown in
Figure 20.
Table 5 lists the required matching components. Capacitors
C1, C2, C3, C4, and C7 are Murata GRM155 series (0402 size)
and Inductor L1 is a Coilcraft 0603CS series (0603 size). For all
frequency bands, the placement of C3 and C7 is critical. From
2500 MHz to 2700 MHz, the placement of C1 is also important.
Table 6 lists the recommended component placement for
various frequencies.
A 5 V dc bias is supplied through L1 that is connected to RFOUT
(Pin 3). In addition to C4, 10 nF and 10 μF power supply
decoupling capacitors are also required. The typical current
consumption for the ADL5321 is 90 mA.
GND VCC
C6 10µF
RFIN C11
λ12
C71
(2)
ADL5321
1
2
3 λ22
C5 10nF
C41
L11
λ32
λ42 C21
C31
RFOUT
1SEE TABLE 5 FOR FREQUENCY SPECIFIC COMPONENTS.
2SEE TABLE 6 FOR RECOMMENDED COMPONENT SPACING.
Figure 20. Basic Connections
Table 5. Recommended Components for Basic Connections
Frequency (MHz)
C1 (pF)
C2 (pF)
2500 to 2700
1.0
10
3400 to 3850
10
10
Table 6. Matching Component Spacing
Frequency (MHz)
2500 to 2700
3400 to 3850
λ1 (mils)
240
90
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 21 shows the recommended land pattern for the ADL5321.
To minimize thermal impedance, the exposed paddle on the
SOT-89 package underside is soldered down to a ground plane
along with (GND) Pin 2. If multiple ground layers exist, they
should be stitched together using vias. For more information on
land pattern design and layout, refer to the AN-772 application
note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
1.80mm
5.56mm 0.20mm
3.48mm
0.86mm
0.62mm
1.27mm
1.50mm
3.00mm
Figure 21. Recommended Land Pattern
C3 (pF)
1.2
1.2
C4 (pF)
10
10
C7 (pF)
Open
1.0
L1 (nH)
9.5
9.5
λ2 (mils)
75
35
λ3 (mils)
89
40
λ4 (mils)
325
416
Rev. 0 | Page 10 of 16
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