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ADIS16266 データシートの表示(PDF) - Analog Devices

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ADIS16266 Datasheet PDF : 24 Pages
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Data Sheet
ADIS16266
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2.
Parameter
Description
Min1
Typ
fSCLK
Serial clock (not shown in figures)
0.01
tDATARATE
Data rate period
32
tSTALL
Stall period between data
9
tCS
Chip select to clock edge
48.8
tDAV
Data output valid after SCLK falling edge2
tDSU
Data input setup time before SCLK rising edge
24.4
tDHD
Data input hold time after SCLK rising edge
48.8
tDF
Data output fall time (not shown in figures)
5
tDR
Data output rise time (not shown in figures)
5
tSFS
CS high after SCLK edge3
5
Max1
Unit
2.5
MHz
µs
µs
ns
100
ns
ns
ns
12.5
ns
12.5
ns
ns
1 Guaranteed by design; not production tested.
2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The remaining DOUT bits are clocked after the falling edge of SCLK
and are governed by this specification.
3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line enters a high impedance state.
Timing Diagrams
CS
tDATARATE
SCLK
tSTALL
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
tCS
1
* MSB
R/W
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
*NOT DEFINED
Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1)
Rev. A | Page 5 of 24

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