EV-ADF4159EB3Z データシートの表示（PDF） - Analog Devices

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EV-ADF4159EB3Z

Direct Modulation/Fast Waveform Generating, 13 GHz, Fractional-N Frequency Synthesizer

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF4159

CPGND 1

AGND 2

AGND 3

RFINB 4

RFINA 5

AVDD 6

ADF4159

TOP VIEW

(Not to Scale)

18 SDVDD

17 MUXOUT

16 LE

15 DATA

14 CLK

13 CE

NOTES

1. THE LFCSP HAS AN EXPOSED PAD

THAT MUST BE CONNECTED TO AGND.

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

CPGND

Charge Pump Ground. This pin is the ground return path for the charge pump.

2, 3

AGND

Analog Ground.

4

RFINB

Complementary Input to the RF Prescaler. Decouple this pin to the ground plane with a small bypass capacitor,

typically 100 pF.

5

RFINA

Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.

6, 7, 8

AVDD

Positive Power Supply for the RF Section. Place decoupling capacitors to the ground plane as close as possible

to these pins.

9

REFIN

Reference Input. This CMOS input has a nominal threshold of DVDD/2 and an equivalent input resistance of 100 kΩ.

It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

10

DGND

Digital Ground.

11

SDGND

Digital Σ-Δ Modulator Ground. This pin is the ground return path for the Σ-Δ modulator.

12

TXDATA

Transmit Data Pin. This pin provides the data to be transmitted in FSK or PSK mode and also controls some

ramping functionality.

13

CE

Chip Enable (1.8 V Logic). A logic low on this pin powers down the device and places the charge pump output

into three-state mode.

14

CLK

Serial Clock Input. This input is used to clock in the serial data to the registers. The data is latched into the input

shift register on the CLK rising edge. This input is a high impedance CMOS input.

15

DATA

Serial Data Input. The serial data is loaded MSB first; the three LSBs are the control bits. This input is a high

impedance CMOS input.

16

LE

Load Enable Input. When LE is high, the data stored in the input shift register is loaded into one of the eight

latches; the latch is selected using the control bits. This input is a high impedance CMOS input.

17

MUXOUT Multiplexer Output. This pin allows various internal signals to be accessed externally.

18

SDVDD

Power Supply for the Digital Σ-Δ Modulator. Place decoupling capacitors to the ground plane as close as

possible to this pin.

19

DVDD

Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close

as possible to this pin.

20, 21

SW1, SW2 Switches for Fast Lock.

22

VP

Charge Pump Power Supply. The voltage on this pin must be greater than or equal to AVDD.

23

RSET

Connecting a resistor between this pin and ground sets the maximum charge pump output current. The

relationship between ICP and RSET is as follows:

ICP_MAX = 24.48/RSET

where:

ICP_MAX = 4.8 mA.

RSET = 5.1 kΩ.

24

CP

Charge Pump Output. When the charge pump is enabled, this output provides ±ICP to the external loop filter,

which, in turn, drives the external VCO.

25

EPAD

Exposed Pad. The LFCSP has an exposed pad that must be connected to AGND.

Rev. B | Page 7 of 36

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