AD9553 データシートの表示（PDF） - Analog Devices
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AD9553
Analog Devices
AD9553 Datasheet PDF : 44 Pages
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AD9553
RESET PIN
Table 4.
Parameter
INPUT CHARACTERISTICS1
Input Voltage High, VIH
Input Voltage Low, VIL
Input Current High, IINH
Input Current Low, IINL
MINIMUM PULSE WIDTH LOW
Min Typ Max Unit
1.96
0.3
31
150
V
0.85 V
12.5 µA
43
µA
µs
1 The RESET pin has a 100 kΩ internal pull-up resistor.
Test Conditions/Comments
Tested with an active source driving the RESET pin
REFERENCE CLOCK INPUT CHARACTERISTICS
Table 5.
Parameter
DIFFERENTIAL INPUT
Input Frequency Range
Min Typ Max
0.008
250
710
Common-Mode Internally Generated 613
Input Voltage
Differential Input Voltage Sensitivity 250
692 769
Differential Input Resistance
Differential Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
CMOS SINGLE-ENDED INPUT
Input Frequency Range
Input High Voltage
Input Low Voltage
Input Threshold Voltage
Input High Current
Input Low Current
Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
×2 FREQUENCY MULTIPLIER
5
3
1.6
1.6
0.64
0.64
0.008
200
1.62
0.52
1.0
0.04
0.03
3
2
2
125
Unit
MHz
MHz
mV
mV p-p
kΩ
pF
ns
ns
ns
ns
MHz
V
V
V
µA
µA
pF
ns
ns
MHz
Test Conditions/Comments
Assumes minimum LVDS input level and requires
bypassing of the divide-by-5 divider and ×2 multiplier
Use ac coupling to preserve the internal dc bias of the
differential input
Requires ac coupling; can accommodate single-ended
input by ac grounding unused input; the instantaneous
voltage on either pin must not exceed the 3.3 V dc supply
rails
Pulse width high and pulse width low specifications
establish the bounds for duty cycle
Up to 250 MHz
Up to 250 MHz
Beyond 250 MHz, up to 710 MHz
Beyond 250 MHz, up to 710 MHz
When ac coupling to the input receiver, the user must dc
bias the input to 1 V; the single-ended CMOS input is 3.3 V
compatible
Pulse width high and pulse width low establish the
bounds for duty cycle
To avoid excessive reference spurs, the ×2 multiplier
requires 48% to 52% duty cycle; reference clock input
frequencies greater than 125 MHz require the use of the
divide-by-5 divider
Rev. A | Page 4 of 44
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