AD9552 データシートの表示（PDF） - Analog Devices
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AD9552 Datasheet PDF : 32 Pages
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Data Sheet
AD9552
By default, a read request reads the register value that is currently
in use by the AD9552. However, setting Register 0x04[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
SCLK
SDIO
13
SERIAL
14 CONTROL
PORT
REGISTER
UPDATE
AD9552
CORE
CS 12
EXECUTE AN
INPUT/OUTPUT
UPDATE
Figure 23. Relationship Between the Serial Control Port Register Buffers and
the Control Registers
The AD9552 uses Register 0x00 to Register 0x34. Although the
AD9552 serial control port allows both 8-bit and 16-bit instruc-
tions, the 8-bit instruction mode provides access to five address
bits (Address Bits[A4:A0]) only, which restricts its use to Address
Space 0x00 to Address Space 0x01. The AD9552 defaults to 16-bit
instruction mode on power-up, and the 8-bit instruction mode
is not supported.
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word (see Table 15) is R/W, which
indicates whether the instruction is a read or a write. The next
two bits, W1 and W0, are the transfer length in bytes. The final
13 bits are the address bits (Address Bits[A12:A0]) at which the
read or write operation is to begin.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted
according to Table 14.
Address Bits[A12:A0] select the address within the register map
that is written to or read from during the data transfer portion
of the communication cycle. The AD9552 uses all of the 13-bit
address space. For multibyte transfers, this address is the starting
byte address.
Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14 I13 I12
I11
I10
I9
I8
R/W
W1 W0 A12 A11 A10 A9 A8
MSB/LSB FIRST TRANSFERS
The AD9552 instruction word and byte data can be MSB first or
LSB first. The default for the AD9552 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x00[6] and requires
that an I/O update be executed. Immediately after the LSB first
bit is set, all serial control port operations are changed to LSB
first order.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB first mode, the serial control port internal address gen-
erator decrements for each data byte of the multibyte transfer cycle.
When LSB first = 1 (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction byte that includes
the register address of the least significant data byte followed
by multiple data bytes. The serial control port internal byte
address generator increments for each data byte of the multibyte
transfer cycle.
The AD9552 serial control port register address decrements from
the register address just written toward 0x00 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the serial control port register address
increments from the address just written toward 0x34 for
multibyte I/O operations.
Unused addresses are not skipped during multibyte I/O operations.
The user should write the default value to a reserved register and
should write only zeros to unmapped registers. Note that it is more
efficient to issue a new write command than to write the default
value to more than two consecutive reserved (or unmapped)
registers.
LSB
I7
I6
I5
I4
I3
I2
I1
I0
A7 A6 A5 A4 A3 A2 A1 A0
Table 16. Definition of Terms Used in Serial Control Port Timing Diagrams
Parameter
Description
tCLK
Period of SCLK
tDV
Read data valid time (time from falling edge of SCLK to valid data on SDIO)
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tS
Setup time between CS and SCLK
tH
Hold time between CS and SCLK
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
Rev. E | Page 21 of 32
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