3
FS = 1V EXT REF
2
1
FS = 1V INT REF
0
–1
–2
–3
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 16. Full-Scale Gain Error vs. Temperature,
AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS, FS = 1
75
SFDR 1V INT REF
70
65
60
55
50
SINAD 1V INT REF
45
40
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 17. SINAD, SFDR vs. Temperature, AIN = 70 MHz @ −1 dBFS, 250 MSPS
0.10
0.05
0
–0.05
–0.10
–0.15
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD (V)
Figure 18. VREF Sensitivity to AVDD
70
65
SFDR
AD9480
60
55
50
SNR
45 SINAD
3.0
3.1
3.2
3.3
3.4
3.5
AVDD (V)
Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage,
AIN = 70.3 MHz @ −1 dBFS, 250 MSPS
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
50
100
150
200
CODE
3.6
250
Figure 20. Typical DNL Plot, AIN = 10.3 MHz @ –0.5 dBFS, 250 MSPS
0.50
0.25
0
–0.25
–0.50
0
50
100
150
200
250
CODE
Figure 21. Typical INL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS
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