AD7746 データシートの表示（PDF） - Analog Devices
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AD7746 Datasheet PDF : 28 Pages
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AD7745/AD7746
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Set-Up Time (Start Condition), tSU;STA
Data Set-Up Time, tSU;DAT
Data Set-Up Time, tSU;DAT
Set-Up Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Condition, tBUF)
Min Typ Max
0
400
0.6
1.3
0.3
0.3
0.6
0.6
0.25
0.35
0.6
0
1.3
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
Test Conditions/Comments
See Figure 3
After this period, the first clock is generated
Relevant for repeated start condition
VDD ≥ 3.0 V
VDD < 3.0 V
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
tLOW tR
tF
tHD:STA
SCL
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
tSU:STO
SDA
tBUF
P
S
S
P
Figure 3. Serial Interface Timing Diagram
Rev. 0| Page 5 of 28
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