AD7691 データシートの表示（PDF） - Analog Devices
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AD7691 Datasheet PDF : 29 Pages
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AD7691
Data Sheet
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
0.5
3.7
µs
Acquisition Time
tACQ
1.8
μs
Time Between Conversions
tCYC
5.5
µs
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
25
ns
SCK Period (Chain Mode)
tSCK
VIO Above 3 V
29
ns
VIO Above 2.7 V
35
ns
VIO Above 2.3 V
40
ns
SCK Low Time
tSCKL
12
ns
SCK High Time
tSCKH
12
ns
SCK Falling Edge to Data Remains Valid
tHSDO
5
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 3 V
24
ns
VIO Above 2.7 V
30
ns
VIO Above 2.3 V
35
ns
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
tEN
VIO Above 2.7 V
18
ns
VIO Above 2.3 V
22
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
30
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
8
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
8
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
10
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
36
1 See Figure 3 and Figure 4 for load conditions.
500µA IOL
TO SDO
CL
50pF
1.4V
500µA IOH
Figure 3. Load Circuit for Digital Interface Timing
30% VIO
tDELAY
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
tDELAY
2V OR VIO – 0.5V1
0.8V OR 0.5V2
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 4. Voltage Levels for Timing
Rev. E | Page 6 of 28
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