AD5429 データシートの表示（PDF） - Analog Devices
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AD5429 Datasheet PDF : 32 Pages
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AD5429/AD5439/AD5449
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1A 1
IOUT2A 2
RFBA 3
VREFA 4
GND 5
LDAC 6
SCLK 7
SDIN 8
AD5429/
AD5439/
AD5449
TOP VIEW
(Not to Scale)
16 IOUT1B
15 IOUT2B
14 RFBB
13 VREFB
12 VDD
11 CLR
10 SYNC
9 SDO
NC = NO CONNECT
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
IOUT1A
DAC A Current Output.
2
IOUT2A
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
3
RFBA
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
4
VREFA
DAC A Reference Voltage Input Pin.
5
GND
Ground Pin.
6
LDAC
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous
update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in
standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
7
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
8
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
9
SDO
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
10
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on
the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched
to the shift register on the16th active clock edge.
11
CLR
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear to zero scale or midscale as required.
12
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
13
VREFB
DAC B Reference Voltage Input Pin.
14
RFBB
DAC B Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
15
IOUT2B
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
16
IOUT1B
DAC B Current Output.
Rev. 0 | Page 8 of 32
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