AD5066 データシートの表示（PDF） - Analog Devices
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AD5066 Datasheet PDF : 24 Pages
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AD5066
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.0 V ≤ VREFA, VREFB, VREFC, VREFD ≤ VDD − 0.4 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Total Unadjusted Error (TUE)
Zero-Code Error
Zero-Code Error Drift3
Full-Scale Error
Gain Error
Gain Error Drift3
DC Crosstalk3
OUTPUT CHARACTERISTICS3
Output Voltage Range
DC Output Impedance (Normal
Mode)
DC Output Impedance
Output Connected to 100 kΩ
Network
Output Connected to 1 kΩ
Network
Power-Up Time4
DC PSRR
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS3
Input Current5
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD
Normal Mode6
All Power-Down Modes7
A Grade1
Min Typ Max
Min
16
16
±0.5 ±4
±0.5 ±4
±0.2 ±1
±0.1 ±0.8
0.05 0.1
±0.5
±0.01 ±0.05
±0.005 ±0.05
±0.5
1
5
5
25
0
8
VREF
0
100
1
2.9
−120
2
VDD − 0.4 2
0.002 ±1
40
±1
0.8
2.2
2.2
4
2.7
5.5
2.7
2.5
3
0.4
B Grade1
Typ Max
Unit Conditions/Comments
±0.5
±0.5
±0.2
±0.1
0.05
±0.5
±0.01
±0.005
±0.5
1
±1
±2
±1
±0.8
0.1
±0.05
±0.05
5
5
25
Bits
LSB
LSB
mV
mV
µV/°C
% FSR
% FSR
ppm
μV
μV
TA = −40°C to +105°C
TA = −40°C to +125°C
VDD = 2.7 V, VREF = 2 V
All 0s loaded to the DAC register
All 1s loaded to the DAC register
ppm of FSR/°C
Due to single-channel full-scale
output change
Due to powering down (per channel)
VREF
V
8
kΩ
100
kΩ
1
kΩ
2.9
µs
−120
dB
VDD − 0.4 V
0.002 ±1
µA
40
MΩ
Output impedance tolerance ± 10%
DAC in power-down mode
Output impedance tolerance ± 20 kΩ
Output impedance tolerance ± 400 Ω
VDD ± 10%, DAC = full scale
Per DAC channel
Per DAC channel
±1
µA
0.8
V
V
4
pF
5.5
2.5
3
0.4
V
All digital inputs at 0 V or VDD
DAC active, excludes load current
VIH = VDD and VIL = GND
mA
µA
1 Temperature range is −40°C to +125°C, typical at 25°C.
2 Linearity calculated using a code range of 0 to 65,535; output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded.
5 Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.
6 Interface inactive. All DACs active. DAC outputs unloaded.
7 All four DACs powered down.
Rev. A | Page 3 of 24
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