AD5040 データシートの表示（PDF） - Analog Devices
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AD5040 Datasheet PDF : 24 Pages
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TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
Limit1
33
5
3
10
3
2
0
12
9
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
SCLK
SYNC
DIN
t4
t8
D23
t2
t1
t3
t6
t5
D22
D2
D1
t9
t7
D0
Figure 2. AD5060 Timing Diagram
AD5040/AD5060
D23
D22
Rev. A | Page 5 of 24
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