AD1985 データシートの表示（PDF） - Analog Devices
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AD1985 Datasheet PDF : 48 Pages
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AD1985
INDEXED CONTROL REGISTERS
Reg Name
D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5 D4 D3 D2
D1 D0 Default
0x00 Reset
X
SE4
SE3 SE2 SE1 SE0 ID9 ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
0x0090
0x02 Master Volume
MM X
X
LMV4 LMV3 LMV2 LMV1 LMV0 MMRM1 X
X
RMV4 RMV3 RMV2 RMV1 RMV0 0x8000
0x04 Headphones Volume HPM X
X
LHV4 LHV3 LHV2 LHV1 LHV0
HPRM1 X
X
RHV4 RHV3 RHV2 RHV1 RHV0 0x8000
0x06 Mono Volume
MVM X
X
X
X
X
X
X
X
X
X
MV4 MV2 MV2
MV1 MV0 0x8000
0x0A PC Beep
PCBM X
X
PCBF7 PCBF6 PCBF5 PCBF4 PCBF3 PCBF2 PCBF1 PCBF0 PCBV3 PCBV2 PCBV1 PCBV0 X
0x8000
0x0C Phone_In Volume
PHM X
X
X
X
X
X
X
X
X
X
PHV4 PHV3 PHV2 PHV1 PHV0 0x8008
0x0E MIC Volume
MCM X
X
X
X
X
X
X
X
M20
X
MCV4 MCV3 MCV2 MCV1 MCV0 0x8008
0x10 Line In Volume
LM
X
X
LLV4 LLV3 LLV2 LLV1 LLV0
LVRM1 X
X
RLV4 RLV3 RLV2 RLV1 RLV0 0x8808
0x12 CD Volume
CM
X
X
LCV4 LCV3 LCV2 LCV1 LCV0
CDRM1 X
X
RCV4 RCV3 RCV2 RCV1 RCV0 0x8808
0x16 AUX In Volume
AM
X
X
LAV4 LAV3 LAV2 LAV1 LAV0
AVRM1 X
X
RAV4 RAV3 RAV2 RAV1 RAV0 0x8808
0x18 PCM Out Vol
OM X
X
LOV4 LOV3 LOV2 LOV1 LOV0
OMRM1 X
X
ROV4 ROV3 ROV2 ROV1 ROV0 0x8808
0x1A Record Select
X
X
X
X
X
LS2 LS1 LS0
X
X
X
X
X
RS2
RS1
RS0
0x0000
0x1C Record Gain
IM
X
X
X
LIV3 LIV2 LIV1 LIV0
IMRM1 X
X
X
RIV3 RIV2
RIV1 RIV0 0x8000
0x20 General Purpose
X
X
X
X
DRSS1 DRSS0 MIX MS
LPBK
X
X
X
X
X
X
X
0x0000
0x24 Audio Int. and Paging I4
I3
I2
I1
I0
X
X
X
X
X
X
X
PG3 PG2
PG1 PG0 0xXXXX
0x26 Power-Down Ctrl/Stat EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0
X
X
X
X
REF
ANL
DAC ADC N/A
0x28 Extended Audio ID AID1 AID0 X
X
REV1 REV0 AMAP AIDLDAC AIDSDAC AIDCDAC DSA1 DSA0 X
AIDSPDIF DRA AIDVRA 0xXBC7
0x2A Ext’d Audio Stat/Ctrl VFORCE X
PRK PRJ PRI SPCV X
ASCLDAC ASCSDAC ASCCDAC SPSA1 SPSA0 X
ASCSPDF ASCDRA ASCVRA 0xXXXX
0x2C PCM Front DAC Rate SRF15 SRF14 SRF13 SRF12 SRF11 SRF10 SRF9 SRF8
SRF7
SRF6
SRF5 SRF4 SRF3 SRF2 SRF1 SRF0 0xBB80
0x2E PCM Surr DAC Rate SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 SRS9 SRS8
SRS7
SRS6
SRS5 SRS4 SRS3 SRS2 SRS1 SRS0 0xBB80
0x30 PCM LFE/C DAC Rate SRCL15 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCL4 SRCL3 SRCL2 SRCL1 SRCL0 0xBB80
0x32 PCM L/R ADC Rate
SRA15 SRA14 SRA13 SRA12 SRA11 SRA10 SRA9 SRA8
SRA7
SRA6
SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 0xBB80
0x36 Center/LFE volume LFEM X
X
LFE4 LFE3 LFE2 LFE1 LFE0
CNTM X
X
CNT4 CNT3 CNT2 CNT1 CNT0 0x8080
0x38 Surround Volume
LSM X
LSR5 LSR4 LSR3 LSR2 LSR1 LSR0
RSM
X
RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 0x8080
0x3A SPDIF Control
V
X
SPSR1 SPSR0 L
CC6 CC5 CC4
CC3
CC2
CC1
CC0
PRE
COPY AUD PRO 0x2000
0x60 EQ Control
EQM X
X
X
X
X
X
X
SYM
CHS
BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 0x8080
0x62 EQ Data
CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0x0000
0x70 J Sense/General
X
X
X
X
X
X
X
X
MMDIS JS2SEL X
X
X
X
X
X
N/A
0x72 J Sense/Audio/Status
JS
SPRD
JS1
DMX
JS0 JS
DMX MT2
JS
MT1
JS
MT0
JS1 JS0
EQB EQB
JS1
JS0
TMR
TMR
JS1
JS0
JS1
JS0
MD
MD
ST
ST
JS1
INT
JS0
INT
N/A
0x74 Serial Configuration SLOT16 REGM2 REGM1 REGM0 REGM3 DRF OMS CHEN SPOVR LBKS1 LBKS0 INTS CSWP SPAL SPDZ SPLNK 0x1001
0x76 Misc Control Bits
DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBG1 MBG0 0x0000
0x78 Advanced Jack Sense X
X
X
X
X
X
X
X
JS3TMR JS2TMR JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT N/A
0x7C Vendor ID1
VIDF7 VIDF6 VIDF5 VIDF4 VIDF3 VIDF2 VIDF1 VIDF0 VIDS7 VIDS6 VIDS5 VIDS4 VIDS3 VIDS2 VIDS1 VIDS0 0x4144
0x7E Vendor ID2
VIDT7 VIDT6 VIDT5 VIDT4 VIDT3 VIDT2 VIDT1 VIDT0 VIDREV7 VIDREV6 VIDREV5 VIDREV4 VIDREV3 VIDREV2 VIDREV1 VIDREV0 0x5375
0x60
pg. 1
Codec Class/Rev
X
X
X
CL4 CL3 CL2 CL1 CL0
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RV0
N/A
0x62
pg. 1
PCI SVID
PVI15 PVI14 PVI13 PVI12 PVI11 PVI10 PVI9 PVI8
PVI7
PVI6
PVI5 PVI4 PVI3 PVI2
PVI1 PVI0 N/A
0x64
pg. 1
PCI SID
PI15 PI14 PI13 PI12 PI11 PI10 PI9 PI8
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
N/A
0x66
pg. 1
Function Select
X
X
X
X
X
X
X
X
X
X
X
FC3
FC2
FC1
FC0
T/R
0x0000
0x68
pg. 1
Function Information
G4
G3
G2
G1
G0
INV DL4 DL3
DL2
DL1
DL0
IV
X
X
X
FIP
N/A
0x6A
pg. 1
Sense Register
ST2 ST1
ST0 S4
S3
S2
S1 S0
NOTES
Odd register addresses are aliased to the next lower even address.
Registers not shown and bits containing an X are assumed to be reserved.
Reserved registers should not be written. Zeros should be written to reserved bits.
OR1
OR0
SR5
SR4
SR3
SR2
SR1
SR0
N/A
1 For AC ‘97 compatibility, these RM bits must be enabled before they can have any effect.
Rev. A | Page 13 of 48
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