AD1940 データシートの表示（PDF） - Analog Devices
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AD1940 Datasheet PDF : 36 Pages
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FEATURES
The core of the AD1940/AD1941 is a 28-bit DSP (56-bit, double
precision) optimized for audio processing. The parts’ program
RAM can be loaded with a custom program after power-up.
Signal processing parameters are stored in a 1024 location
parameter RAM, which is initialized on power-up by an internal
boot ROM. New values are written to the parameter RAM using
the control port. The values stored in the parameter RAM
control individual signal processing blocks, such as IIR equali-
zation filters, dynamics processors, audio delays, and mixer
levels. A safeload feature allows parameters to be transparently
updated without causing clicks on the output signals.
The target/slew RAM contains 64 locations and can be used as
channel volume controls or for other parameter updates. These
RAM locations take a target value for a given parameter and
ramp the current parameter value to the new value using a
specified time constant and one of a selection of linear or
logarithmic curves.
The AD1940/AD1941 contain eight independent data capture
circuits that can be programmed to tap the signal flow of the
processor at any point in the DSP algorithm flow. Six of these
captured signals can be accessed by reading from the data
capture registers through the control port. The remaining two
data capture registers can be used to send any internal captured
signal to a stereo digital output signal on Pin SDATA_OUT7 for
driving external DACs or digital analyzers.
AD1940/AD1941
The AD1940/AD1941 have a sophisticated control port that
supports complete read/write capability of all memory
locations. Five control registers (Core, RAM configuration,
Serial Output 0 to 7, Serial Output 8 to 15, and serial input) are
provided to offer complete control of the chip’s configuration
and serial modes. Handshaking is included for ease of memory
uploads/downloads. The AD1940 is SPI-controlled and the
AD1941 is controlled by an I2C bus.
The AD1940/AD1941 have very flexible serial data input/output
ports that allow glueless interconnection to a variety of ADCs,
DACs, general-purpose DSPs, S/PDIF receivers and trans-
mitters, and sample rate converters. The AD1940/AD1941 can
be configured in I2S, left-justified, right-justified, or TDM serial
port-compatible modes. It can support 16, 20, and 24 bits in all
modes. The AD1940/AD1941 accepts serial audio data in MSB
first and twos complement format.
A master clock phase-locked loop (PLL) allows the AD1940/
AD1941 to be clocked from a variety of different clock speeds.
The PLL can accept inputs of 64 × fS, 256 × fS, 384 × fS, or 512 ×
fS to generate the core’s internal master clock.
The AD1940/AD1941 operate from a single 2.5 V power supply.
An on-board voltage regulator can be used to operate the chip
with 3.3 V or 5 V supplies. They are fabricated on a single
monolithic integrated circuit and are housed in 48-lead
LQFP packages for operation over the –40°C to +105°C
temperature range.
SERIAL
DATA/TDM
INPUT
GROUP
PLL MODE
SELECT
MASTER
CLOCK
INPUT
CONTROL PORT
I/O GROUP
ADDRESS SELECT
RESETB
DATA MEMORY
6k × 28
TARGET/SLEW
RAM
2
64 × 28
2
MCLK
PLL
CONTROL
REGISITER
4
SERIAL
CONTROL TRAP REG.
PORT
SAFELOAD
REGISTER
28 × 28
DSP CORE
DATA FORMAT:
5.23 (SINGLE PRECISION)
10.46 (DOUBLE PRECISION)
2
2
SERIAL DATA/
TDM OUTPUT
GROUP
PROGRAM
RAM
1536 × 40
PARAMETER
RAM
1024 × 28
COEFFICIENT
ROM
512 × 28
MEMORY CONTROLLERS
VOLTAGE REGULATOR
4
REGULATOR
GROUP
Figure 9. Block Diagram
Rev. A | Page 11 of 36
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