AD1833 データシートの表示（PDF） - Analog Devices

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AD1833

Multichannel, 24-Bit, 192 kHz,
- DAC

Analog Devices 

MCLK Select

The AD1833 allows the matching of available external MCLK

frequencies to the required sample rate. The oversampling rate

can be selected from 256 × fS, 512 × fS or 768 × fS by writing to

Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of

512 × fS; therefore, in the case of 256 × fS mode, a clock doubler

is used, whereas in 768 × fS mode, a divide-by-3 block (/3) is

first implemented, followed by a clock doubler. See Table XII.

Bit 4

0

0

1

1

Table XII. MCLK Settings

Bit 3

0

1

0

1

Oversample Ratio

256 × fS (MCLK × 2 Internally)

512 × fS

768 × fS (MCLK × 2/3 Internally)

Reserved

Channel Zero Status

The AD1833 provides individual logic output status indicators

when zero data is sent to a channel for 1024 or more consecutive

sample periods. There is also a global zero flag that indicates all

channels contain zero data. The polarity of the active zero signal

AD1833

is programmable by writing to Control Bit 2, see Table XIII.

The six individual channel flags are best used as three stereo

zero flags by combining pairs of them through suitable logic

gates. Then, when both the left and right input are zero for 1024

clock cycles, i.e., a stereo zero input for 1024 sample periods,

the combined result of the two individual flags will go active

indicating a stereo zero.

Table XIII. Zero Detect

Bit 2

Channel Zero Status

0

Active High

1

Active Low

DAC Volume Control Registers

The AD1833 has six volume control registers, one each for the

six DAC channels. Volume control is exercised by writing to the

relevant register associated with each DAC. This setting is used

to attenuate the DAC output. Full-scale setting (all 1s) is equiva-

lent to zero attenuation. See Table XV.

Sampling Rate fS (kHz)

32

64

128

44.1

88.2

176.4

48

96

192

Table XIV. MCLK vs. Sample Rate Selection

Interpolator Mode

8× (Normal)

4× (Double)

2× (4 Times)

8× (Normal)

4× (Double)

2× (4 Times)

8× (Normal)

4× (Double)

2× (4 Times)

256 fS

8.192

11.2896

12.288

MCLK (MHz)

512 fS

16.384

22.5792

24.576

768 fS

24.576

33.8688

36.864

Table XV. Volume Control Registers

Address

Reserved*

15–12

11

10

0010 0

0

0011

0100

0101

0110

0111

*Must be programmed to zero.

Volume Control

9–0

Channel 1 Volume Control (OUTL1)

Channel 2 Volume Control (OUTR1)

Channel 3 Volume Control (OUTL2)

Channel 4 Volume Control (OUTR2)

Channel 5 Volume Control (OUTL3)

Channel 6 Volume Control (OUTR3)

REV. 0

–11–

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