ACT5880 データシートの表示（PDF） - Active-Semi, Inc
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ACT5880 Datasheet PDF : 87 Pages
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ACT5880
Rev 2, 03-Sep-13
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
E8
SW2 The Switch Node of the Step-down DC/DC REG2. Same function as pin E9.
E9
SW2 The Switch Node of the Step-down DC/DC REG2. Same function as pin E8.
The Ground Path of the Step-down DC/DC REG1. Provide the direct ground return path between
F1
GP1 the internal switch, the external storage capacitor and the input decoupling capacitor. Same function
as pin G3.
The Open Drain Output 1. A current driver output with programmable output current. It could operate
F2 ODO1 in constant current mode, switch on/off mode or PWM mode. The maximum voltage is 40V for this
pin.
F3 OUT13 The Output of the LDO REG13. Bypass to GA with a 1.5μF high quality ceramic capacitor.
F4
INL1213
The Input Node for the LDO REG12 and REG13. Bypass to GA with a 1μF high quality ceramic
capacitor.
F5
GA
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2 and GP3 to a
single point as close to the IC as possible.
F6
REFBP
The Reference Bypass Node. Bypass to GA with a 47nF capacitor for noise suppression and PSRR
performance improvement. This pin is discharged to GA in shutdown.
F7
OUT2 The Step-down DC/DC REG2 Feedback Node. Connect it to the output node of REG2.
F8
VP2 The Switch Power Input Node of the Step-down DC/DC REG2. Same function as pin F9.
F9
VP2 The Switch Power Input Node of the Step-down DC/DC REG2. Same function as pin F8.
G1
SW1 The Switch Node of the Step-down DC/DC REG1. Same function as pin G2 and pin H1.
G2
SW1 The Switch Node of the Step-down DC/DC REG1. Same function as pin G1 and pin H1.
G3
GP1 The Ground Path of the Step-down DC/DC REG1. Same function as pin F1.
G4 OUT12 The Output of the LDO REG12. Bypass to GA with a 2.2μF high quality ceramic capacitor.
G5
VSYS
The Internal Bias Bypass. This rail is available all time that this IC works, bypass to GA with a 1μF
high quality ceramic capacitor.
G6
VD
The Power Input for Biasing the ADC Circuit. Bypass to GD with a 100nF high quality ceramic
capacitor.
G7
XNEG
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node XNEG with an
internal force switch.
G8
YPOS
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node YPOS with an
internal force switch.
G9
YNEG
One of ADC Input, Internally Configured as the Touch Screen Force-Sense Node YNEG with an
internal force switch.
H1
SW1 The Switch Node of the Step-down DC/DC REG1. Same function as pin G1 and pin G2.
H2
VP1 The Switch Power Input Node of the Step-down DC/DC REG1. Same function as pin J2.
H3
VSEL
The Output Voltage Selection Input for the Step-down DC/DC REG1. Allow the output voltage of the
step-down DC/DC REG1 flies between 2 preset voltages by asserting different logic level at this pin.
H4
SCL
The Clock for the I2C compatible Serial Interface. Does the same function as the SCL of a normal
400kHz fast I2C slave device.
H5
SDA
The Data for the I2C compatible Serial Interface. Does the same function as the SDA of a normal
400kHz fast I2C slave device.
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I2CTM is a trademark of NXP.
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Copyright © 2013 Active-Semi, Inc.
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