A3907 データシートの表示（PDF） - Allegro MicroSystems
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A3907 Datasheet PDF : 11 Pages
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A3907
Low Voltage Voice Coil Motor Driver
I2C Interface
This is a serial interface that uses two bus lines, SCL and SDA, to
access the internal control registers. Data is exchanged between a
microcontroller (master) and the A3907 (slave). The clock input
to SCL is generated by the master, while SDA functions as either
an input or an open drain output, depending on the direction of
the data. The I2C input thresholds do not depend on the VDD
voltage of the A3907. The levels are fixed at approximately 1V.
The fixed levels allow the SDA and SCL lines to be pulled-up to
a different logic level than the VDD supply of the 3907.
Timing Considerations The control sequence of the commu-
nication through the I2C interface is composed of several steps in
sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate write (0)
or read(1), and an acknowledge bit. The address setting is 0x18,
0x1A, 0x1C, or 0x1E.
3. Data Cycles. Write requires 7 bits of address data selecting the
internal control register, followed by an acknowledge bit.
4. Stop Condition. Defined by a positive edge on the SDA line,
while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low. It is possible for the Start or Stop condition to occur at any
time during a data transfer. The A3907 always responds by reset-
ting the data transfer sequence.
To indicate a write cycle, the Read/Write bit is set to low.
Mulitple writes are allowed. If desired, the readback bit can be set
to high to check what was last written.
The Acknowledge bit is used by the master to determine if the
slave device is responding to its address and data transmis-
sions. When the A3907 decodes the 7-bit address field as a valid
address, it responds by pulling SDA low during the ninth clock
cycle.
During a data write from the master, the A3907 pulls SDA low
during the clock cycle that follows the last data byte, in order
to indicate that the data has been successfully received. In both
cases, the master device must release the SDA line before the
ninth clock cycle, in order to allow this handshaking to occur.
Slave (A3907) Address
Device Identifier
R/W
0
0
0
1
1
X
X
0
Control Register MS Byte (I2C Write register)
Bit
Name
Function
0
D4
DAC
1
D5
DAC
2
D6
DAC
3
D7
DAC
4
D8
DAC
5
D9
DAC MSB
6
T5
Not used
7
SLEEP
1=Sleep 0=Normal
Control Register MS Byte (I2C Write register)
Bit
Name
Function
0
T0
Time Setting LSB
1
T1
Time Setting Bit 1
2
T2
Time Setting Bit2
3
T3
Time Setting Bit 3
4
D0
DAC LSB
5
D1
DAC
6
D2
DAC
7
D3
DAC
Write Operation
Allegro MicroSystems, LLC
7
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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