88SM4140 データシートの表示（PDF） - Marvell Semiconductor

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88SM4140

Serial ATA 3.0 Gbps: 1-to-4 Port Multiplier

Marvell Semiconductor 

88SM4140 Preliminary Specifications

Serial ATA 3.0 Gbps: 1-to-4 Port Multiplier

CONTENTS

1 OVERVIEW ................................................................................................................................................ 1-1

2 FEATURES ................................................................................................................................................ 2-1

2.1 GENERAL .......................................................................................................................................... 2-1

2.2 FUNCTIONAL ...................................................................................................................................... 2-1

3 PACKAGE ................................................................................................................................................. 3-1

3.1 PACKAGE PIN-OUT ............................................................................................................................ 3-2

3.2 PACKAGE DIMENSIONS ....................................................................................................................... 3-3

3.3 PIN DESCRIPTIONS ............................................................................................................................ 3-6

3.3.1 Pin Type Definitions .......................................................................................................... 3-6

3.3.2 Pin List .............................................................................................................................. 3-6

4 MARVELL-SPECIFIC MODE ..................................................................................................................... 4-1

4.1 MARVELL-SPECIFIC MODE ................................................................................................................. 4-1

5 PCB LAYOUT GUIDELINES ..................................................................................................................... 5-1

5.1 TRANSMIT/RECEIVE DIFFERENTIAL PAIRS INTERFACE .......................................................................... 5-2

5.1.1 Differential Impedance ...................................................................................................... 5-2

5.1.2 Impedance ........................................................................................................................ 5-2

5.1.3 Minimizing Skew ............................................................................................................... 5-3

5.1.4 Using Vias With TX/RX Differential Pairs .......................................................................... 5-3

5.1.5 AC-Coupled SATA Signals ............................................................................................... 5-4

5.2 DC POWER AND GROUND .................................................................................................................. 5-5

5.2.1 VDD Power (1.2V) and GND ............................................................................................. 5-5

5.2.2 VDDIO Power (3.3V) and GND (or ePAD GND) ............................................................... 5-5

5.2.3 VAA Power (3.3V) and ePAD (VSS) ................................................................................. 5-5

5.3 EXPOSED DIE PAD PACKAGE DESIGN ................................................................................................. 5-6

5.4 LAYER STACK-UP/SIGNAL RETURN PATH ........................................................................................... 5-8

5.5 DESIGN GUIDELINES .......................................................................................................................... 5-9

5.5.1 General ............................................................................................................................. 5-9

5.5.2 Vias ................................................................................................................................... 5-9

5.5.3 Traces ............................................................................................................................... 5-9

5.5.4 Signal Routing ................................................................................................................... 5-9

5.5.5 Planes ............................................................................................................................... 5-10

5.5.6 Clock ................................................................................................................................. 5-10

5.5.7 Bias Current Resistor (ISET) ............................................................................................. 5-10

5.5.8 Power-on-Reset Signal ..................................................................................................... 5-11

5.5.9 UART Interface ................................................................................................................. 5-11

5.5.10 Ground for SATA Connector ............................................................................................. 5-11

6 UART INTERFACE .................................................................................................................................... 6-1

6.1 UART INTERFACE TIMING EXAMPLE ................................................................................................... 6-2

Copyright © 2007 Marvell Technology Group, Ltd.

Do not duplicate without permission. Document Classification: Proprietary

vii

February 1, 2007

Doc No. MV-S101553-00 Rev. G

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