7C132-25 データシートの表示（PDF） - Cypress Semiconductor

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7C132-25

2Kx8 Dual-Port Static RAM

Cypress Semiconductor 

Switching Waveforms

Read Cycle No. 1 (Either Port-Address Access)[20, 21]

ADDRESS

DATA OUT

tOHA

PREVIOUS DATA VALID

tRC

tAA

Read Cycle No. 2 (Either Port-CE/OE)[20, 22]

CY7C132/CY7C136

CY7C142/CY7C146

DATA VALID

C132-7

CE

OE

DATA OUT

ICC

ISB

tACE

tLZCE

tLZOE

tDOE

tPU

tHZOE

tHZCE

DATA VALID

tPD

C132-8

Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)

n

tRC

ADDRESSR

ADDRESS MATCH

R/WR

tPWE

DINR

ADDRESSL

BUSYL

DOUTL

tPS

tBLA

Notes:

20. R/W is HIGH for read cycle.

21. Device is continuously selected, CE = VIL and OE = VIL.

22. Address valid prior to or coincident with CE transition LOW.

VALID

ADDRESS MATCH

tBHA

tWDD

tDDD

tBDD

VALID

C132-9

7

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