![](/html/Fairchild/250364/page2.png)
Connection Diagram
Logic Symbol/s
IEEE/IEC
Pin Descriptions
Pin Names
CLR1, CLR2
CP1, CP2
QA, QB, QC, QD
Description
Clear Inputs
Clock Pulse Inputs
Outputs
System Diagram
Truth Table
Inputs
Outputs
CP
CLR QA QB QC QD
X
H
L
L
L
L
L
Count Up
L
No Change
X: Don’t Care
©1998 Fairchild Semiconductor Corporation
74VHC393 Rev. 1.4
2
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