74LCX374(2013) データシートの表示（PDF） - Fairchild Semiconductor

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74LCX374
(Rev.:2013)

Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs

Fairchild Semiconductor 

Connection Diagrams

Pin Assignments for

SOIC, SOP, SSOP, TSSOP

OE 1

O0 2

D0 3

D1 4

O1 5

O2 6

D2 7

D3 8

O3 9

GND 10

20 VCC

19 O7

18 D7

17 D6

16 O6

15 O5

14 D5

13 D4

12 O4

11 CP

Pad Assignments for DQFN

OE VCC

1 20

O0 2

19 O7

D0 3

18 D7

D1 4

17 D6

O1 5

16 O6

O2 6

15 O5

D2 7

14 D5

D3 8

13 D4

O3 9

12 O4

10 11

GND CP

(Top View)

(Bottom View)

Pin Description

Pin Names

Description

D0–D7

CP

Data Inputs

Clock Pulse Input

OE

Output Enable Input

O0–O7

3-STATE Outputs

DAP

No Connect

Note: DAP (Die Attach Pad)

Logic Symbol

D0 D1 D2 D3 D4 D5 D6 D7

CP

OE

O0 O1 O2 O3 O4 O5 O6 O7

Truth Table

Inputs

Outputs

Dn

CP

OE

On

H

L

H

L

L

L

X

L

L

O0

X

X

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

= LOW-to-HIGH Transition

O0 = Previous O0 before HIGH-to-LOW of CP

Functional Description

The LCX374 consists of eight edge-triggered flip-flops

with individual D-type inputs and 3-STATE true outputs.

The buffered clock and buffered Output Enable are com-

mon to all flip-flops. The eight flip-flops will store the

state of their individual D inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CP)

transition. With the Output Enable (OE) LOW, the con-

tents of the eight flip-flops are available at the outputs.

When the OE is HIGH, the outputs go to the high imped-

ance state. Operation of the OE input does not affect the

state of the flip-flops.

Please note that this diagram is provided only for the

understanding of logic operations and should not be

used to estimate propagation delays.

©2006 Fairchild Semiconductor Corporation

74LCX374 Rev. 1.6.1

2

www.fairchildsemi.com

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