GS881E18AT-250 データシートの表示（PDF） - Giga Semiconductor

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GS881E18AT-250

512K x 18, 256K x 36 9Mb Sync Burst SRAMs

Giga Semiconductor 

Preliminary

GS881E18/36AT-250/225/200/166/150/133

Pipelined DCD Read Cycle Timing

CK

ADSP

ADSC

ADV

A0–An

GW

BW

Single Read

tS tH

Burst Read

tKL

tKH

tKC ADSP is blocked by E1 inactive

tS tH ADSC initiated read

tS tH

Suspend Burst

tS tH

RD1

tS

RD2

RD3

tH

tS

tH

BA–BD

E1

G

DQA–DQD

tS tH

tOE

tOLZ

Hi-Z

tLZ

tOHZ

Q1A

tKQ

E1 masks ADSP

tKQX

Q2A Q2B

Q2c

Q2D

tKQX

Q3A

tHZ

Rev: 1.01 3/2002

20/34

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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