3507 データシートの表示（PDF） - Linear Technology

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3507

Triple Monolithic Step-Down Regulator with LDO

Linear Technology 

LT3507

APPLICATIONS INFORMATION

STEP-DOWN CONSIDERATIONS

FB Resistor Network

The output voltage is programmed with a resistor divider

(refer to the Block Diagram) between the output and the

FB pin. Choose the resistors according to:

R1=

R2


VOUT

800mV

–

1

The parallel combination of R1 and R2 should be 10k or

less to avoid bias current errors.

Input Voltage Range

The minimum operating voltage is determined either by

the LT3507’s internal undervoltage lockout (4V on VIN1, 3V

on VIN2 and VIN3) or by its maximum duty cycle. The duty

cycle is the fraction of time that the internal switch is on

and is determined by the input and output voltages:

DC =

VOUT + VF

VIN – VSW +

VF

where VF is the forward voltage drop of the catch diode

(~0.4V) and VSW is the voltage drop of the internal switch

(~0.3V at maximum load). This leads to a minimum input

voltage of:

VIN(MIN) =

VOUT + VF

DCMAX

– VF

+ VSW

The duty cycle is the fraction of time that the internal

switch is on during a clock cycle. The maximum duty cycle

is generally given by DCMAX = 1– tOFF(MIN)• fSW. However,

unlike most fixed frequency regulators, the LT3507 will not

switch off at the end of each clock cycle if there is sufficient

voltage across the boost capacitor (C3 in Figure 1) to fully

saturate the output switch. Forced switch off for a minimum

time will only occur at the end of a clock cycle when the

boost capacitor needs to be recharged. This operation

has the same effect as lowering the clock frequency for a

fixed off time, resulting in a higher duty cycle and lower

minimum input voltage. The resultant duty cycle depends

on the charging times of the boost capacitor and can be

approximated by the following equation:

10

DCMAX

=

1

1+

1

B

where B is the output current capacity divided by the typical

boost current from the BOOST pin current vs switch current

in the Typical Performance Characteristics section.

The maximum operating voltage without pulse skipping

is determined by the minimum duty cycle DCMIN:

VIN(PS)

=

VOUT + VF

DCMIN

–

VF

+ VSW

with DCMIN = tON(MIN) • fSW.

Thus both the maximum and minimum input voltages are

a function of the switching frequency and output voltages.

Therefore the maximum switching frequency must be set

to a value that accommodates all the input and output

voltage parameters and must meet both of the following

criteria for each channel:

fMAX1

=



VOUT + VF

VIN(PS) – VSW +

VF







•

1

tON(MIN)

fMAX2

=  1–



VOUT

VIN(MIN) –

+ VF

VSW

+

VF







•

1

tOFF(MIN)

The values of tON(MIN) and tOFF(MIN) are functions of ISW

and temperature (see chart in the Typical Performance

Characteristics section). Worst-case values for switch

currents greater than 0.5A are tON(MIN) = 130ns (for TJ >

125°C tON(MIN) = 155ns) and tOFF(MIN) = 170ns.

fMAX1 is the frequency at which the minimum duty cycle

is exceeded. The regulator will skip ON pulses in order to

reduce the overall duty cycle at frequencies above fMAX1.

It will continue to regulate but with increased inductor

current and greatly increased output ripple. The increased

peak inductor current in pulse skipping will also stress

the switch transistor at high voltages and high switch-

ing frequency. If the LT3507 is allowed to pulse skip and

the input voltage is greater than 20V, then the switching

frequency must be kept below 1.1MHz to prevent damage

to the LT3507.

3507f

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