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V827464N24S データシートの表示(PDF) - Mosel Vitelic Corporation

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V827464N24S Datasheet PDF : 15 Pages
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MOSEL VITELIC
Serial Presence Detect Information (cont.)
V827464N24S
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 C0 A1 B0 B1 C0
28 Minimum row activate to row active delay(=tRRD)
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module Row density
15ns 15ns 15ns 12ns 3Ch 3Ch 38h 30h
20ns 20ns 20ns 18ns 50h 50h 48h 48h
50ns 45ns 45ns 42ns 32h 2Dh 2Dh 2Ah
256MB
40h
32 Command and address signal input setup time
1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h
33 Command and address signal input hold time
1.1ns 0.9ns 0.9ns 0.75ns B0h 90h 90h 75h
34 Data signal input setup time
0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h
35 Data signal input hold time
0.6ns 0.5ns 0.5ns 0.45ns 60h 50h 50h 45h
36-40 Superset information (may be used in future)
-
00h
41 SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns 65ns 65ns 60ns 46h 41h 3Ch 3Ch
42 SDRAM device minimum active to autorefresh to active/auto-re- 80ns 75ns 75ns 72ns 50h 4Bh 4Bh 48h
fresh time (=tRFC)
43 SDRAM device maximum device cycle time (=tCK MAX)
12ns 12ns 12ns 12ns 30h 30h 30h 30h
44 SDRAM device maximum skew between DQS and DQ signals 0.6ns 0.5ns 0.5ns 0.45ns 3Ch 32h 32h 2Dh
(=tDQSQ)
45 SDRAM device maximum read datahold skew factor (=tQHS)
1ns 0.75ns 0.75ns 0.60ns A0h 75h 75h 60h
62 SPD data revision code
Initial release
00h
63 Checksum for Bytes 0 ~ 62
-
38h 73h 2Ah 9Ch
64 Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71 ....... Manufacturer JEDEC ID code
00h
72 Manufacturing location
02=Taiwan 05=China
0A=S-CH
73-90 Module part number (ASCII)
V827464N24S
91 Manufacturer revison code (For PCB)
0
00
92 Manufacturer revison code (For component)
0
00
93 Manufacturing date (Week)
-
-
94 Manufacturing date (Year)
-
-
95~98 Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~25 Open for customer use
5
Undefined
00h
V827464N24S Rev. 1.0 August 2002
6

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