28F128 データシートの表示（PDF） - Intel
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28F128 Datasheet PDF : 58 Pages
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28F128J3A, 28F640J3A, 28F320J3A
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS pin to be configured to pulse
on completion of programming and/or block erases.
Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2,
“Chip Enable Truth Table” on page 7) reduces decoder logic typically required for multi-chip
designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit
mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit
operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A
device block diagram is shown in Figure 1 on page 2.
When the device is disabled (see Table 2 on page 7) and the RP# pin is at VCC, the standby mode is
enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (tPHQV) is required
from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL)
from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the
status register is cleared.
3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP
(Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities.
Figure 2 and Figure 3 show the pinouts.
Figure 1. 3 Volt Intel® StrataFlash™ Memory Block Diagram
DQ0 - DQ15
VCCQ
A0- A2
32-Mbit: A0- A21
64-Mbit: A0 - A22
128-Mbit: A0 - A23
Input Buffer
Address
Latch
Address
Counter
Y-Decoder
X-Decoder
Output
Buffer
Input Buffer
Query
Identifier
Register
Status
Register
Data
Comparator
Multiplexer
Y-Gating
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
128-Kbyte Blocks
Command
User
Interface
I/O Logic
CE
Logic
VCC
BYTE#
CE0
CE1
CE2
WE#
OE#
RP#
Write State
Machine
Program/Erase
Voltage Switch
STS
VPEN
VCC
GND
2
Preliminary
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