28F016SV FlashFile™ MEMORY
DQ
8-15
DQ
0-7
E
Output
Buffer
Input
Buffer
Address
Queue
Registers
Y
Decoder
X
Decoder
Address
Counter
Output
Buffer
ID
Register
CSR
Input
Buffer
Data
Queue
Registers
Input
Buffer
I/O Logic
3/5#
BYTE#
Page
Buffers
ESRs
Data
Comparator
Y Gating/Sensing
CE0#
CE1#
OE#
WE#
WP#
RP#
RY/BY#
Program/Erase
Voltage Switch
V PP
3/5#
VCC
GND
0528_01
Figure 1. 28F016SV Block Diagram
Architectural Evolution Includes SmartVoltage Technology,
Page Buffers, Queue Registers and Extended Registers
10