MC10EL34DR2(2000) データシートの表示（PDF） - ON Semiconductor

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MC10EL34DR2
(Rev.:2000)

5V ECL ÷2, ÷4, ÷8 Clock Generation Chip

ON Semiconductor 

MC10EL34, MC100EL34

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

VCC EN NC CLK CLK VBB MR VEE

16 15 14 13 12 11 10 9

D

QR

CLK*

FUNCTION TABLE

EN*

MR*

FUNCTION

÷2

QR

÷4

QR

÷8

QR

Z

L

ZZ

H

X

X

L

Divide

L

Hold Q0–3

H

Reset Q0–3

12345678

Q0 Q0 VCC Q1 Q1 VCC Q2 Q2

* All VCC pins are tied together on the die.

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Z = Low-to-High Transition

ZZ = High-to-Low Transition

* Pins will default low when left open.

PIN DESCRIPTION

PIN

CLK, CLK

EN

MR

Q0, Q0

Q1, Q1

Q2, Q2

VBB

VCC

VEE

NC

FUNCTION

ECL Diff Clock Inputs

ECL Sync Enable

ECL Master Reset

ECL Diff ÷2 Outputs

ECL Diff ÷4 Outputs

ECL Diff ÷8 Outputs

Reference Voltage Output

Positive Supply

Negative Supply

No Connect

MAXIMUM RATINGS (Note 1.)

Symbol

Parameter

Condition 1

Condition 2

VCC

PECL Mode Power Supply

VEE

NECL Mode Power Supply

VI

PECL Mode Input Voltage

NECL Mode Input Voltage

Iout

Output Current

VEE = 0 V

VCC = 0 V

VEE = 0 V

VCC = 0 V

Continuous

Surge

VI  VCC

VI  VEE

IBB

VBB Sink/Source

TA

Operating Temperature Range

Tstg

Storage Temperature Range

θJA

Thermal Resistance (Junction to Ambient) 0 LFPM

500 LFPM

16 SOIC

16 SOIC

θJC

Thermal Resistance (Junction to Case)

std bd

Tsol

Wave Solder

<2 to 3 sec @ 248°C

1. Maximum Ratings are those values beyond which device damage may occur.

16 SOIC

Rating

8

–8

6

–6

50

100

± 0.5

–40 to +85

–65 to +150

130

75

33 to 36

265

Units

V

V

V

V

mA

mA

mA

°C

°C

°C/W

°C/W

°C/W

°C

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