10XS4200 データシートの表示（PDF） - Freescale Semiconductor

部品番号

コンポーネント説明

一致するリスト

10XS4200

Dual 24 V, 10 mOhm High Side Switch

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Unless specified otherwise: 8.0 V ≤ VPWR ≤ 36 V, 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 125 °C, GND = 0 V. Typical values are

average values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V & VDD = 5.0 V, unless specified otherwise.

Parameter

Symbol

Min

Typ

Max

Unit

SPI INTERFACE ELECTRICAL CHARACTERISTICS(38)

Maximum Operating Frequency of the Serial Peripheral Interface (SPI)(44)

Required Low-state Duration for reset RSTB(39)

f SPI

–

–

8.0

MHz

t WRSTB

10

–

–

μs

Required duration from the Rising to the Falling Edge of CSB (Required Setup

Time)(40)

t CSB

1.0

–

–

μs

Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)(40)

Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(40)

Required High State Duration of SCLK (Required Setup Time)(40)

Required Low State Duration of SCLK (Required Setup Time)(40)

Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)(40)

SI to Falling Edge of SCLK (Required Setup Time)(41)

Falling Edge of SCLK to SI (Required Setup Time)(41)

SO Rise Time

CL = 80 pF

t ENBL

5.0

–

t LEAD

500

–

t WSCLKh

50

–

t WSCLKl

50

–

t LAG

60

–

t SI (SU)

37

–

t SI (HOLD)

49

–

t RSO

–

–

–

μs

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

20

ns

SO Fall Time

CL = 80 pF

t FSO

–

–

20

ns

SI, CSB, SCLK, Max. Rise Time allowing operation at fSPI = 8.0 MHz(41)

SI, CSB, SCLK, Max. Fall Time allowing operation at fSPI = 8.0 MHz(41)

Time from Rising Edge of SCLK to the SO Low-level(42)

Time from Rising Edge of SCLK to the SO High-level(43)

t RSI

–

–

12

ns

t FSI

–

–

12

ns

t SO(EN)

–

–

73

ns

t SO(DIS)

–

–

73

ns

Notes

38. Parameters guaranteed by design. It is recommended to tie unused SPI pins to GND with resistors 1.0k < R <10 k

39. RSTB low duration defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs

inactive).

40. Minimum setup time required for the device is the minimum required time that the microcontroller must wait or remain in a given state.

41. Rise and Fall time of incoming SI, CSB, and SCLK signals.

42. Time required for output data to be available for use at SO, measured with a 1.0 kΩ series resistor connected CSB.

43. Time required for output data to be terminated at SO measured with a 1.0 kΩ series resistor connected CSB.

44. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V)

ceramic speed-up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, and CS.

Analog Integrated Circuit Device Data

Freescale Semiconductor

10XS4200

19

Share Link: