10XS3435(2009) データシートの表示（PDF） - Freescale Semiconductor

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10XS3435
(Rev.:2009)

Quad High Side Switch (Dual 10 mOhm, Dual 35 mOhm)

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SPI INTERFACE CHARACTERISTICS(39)

Maximum Frequency of SPI Operation

Required Low State Duration for RST(40)

Rising Edge of CS to Falling Edge of CS (Required Setup Time)(41)

Rising Edge of RST to Falling Edge of CS (Required Setup Time)(41)

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(41)

Required High State Duration of SCLK (Required Setup Time)(41)

Required Low State Duration of SCLK (Required Setup Time)(41)

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(41)

SI to Falling Edge of SCLK (Required Setup Time)(42)

Falling Edge of SCLK to SI (Required Setup Time)(42)

SO Rise Time

CL = 80 pF

f SPI

–

t WRST

10

t CS

–

t ENBL

–

t LEAD

–

t WSCLKh

–

t WSCLKl

–

t LAG

–

t SI (SU)

–

t SI (HOLD)

–

t RSO

–

–

8.0

MHz

–

–

μs

–

1.0

μs

–

5.0

μs

–

500

ns

–

50

ns

–

50

ns

–

60

ns

–

37

ns

–

49

ns

ns

–

13

SO Fall Time

CL = 80 pF

t FSO

–

ns

–

13

SI, CS, SCLK, Incoming Signal Rise Time(42)

SI, CS, SCLK, Incoming Signal Fall Time(42)

Time from Falling Edge of CS to SO Low-impedance(43)

Time from Rising Edge of CS to SO High-impedance(44)

t RSI

–

t FSI

–

t SO(EN)

–

t SO(DIS)

–

–

13

ns

–

13

ns

–

60

ns

–

60

ns

Notes

39. Parameters guaranteed by design.

40. RST low duration measured with outputs enabled and going to OFF or disabled condition.

41. Maximum setup time required for the 10XS3435 is the minimum guaranteed time needed from the microcontroller.

42. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

43. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.

44. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.

10XS3435

20

Analog Integrated Circuit Device Data

Freescale Semiconductor

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