MT28S2M32B1LC データシートの表示（PDF） - Micron Technology

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MT28S2M32B1LC

SYNCFLASH® MEMORY

Micron Technology 

GENERAL DESCRIPTION

This 64Mb SyncFlash® data sheet is divided into

two major sections. The SDRAM Interface Functional

Description details compatibility with the SDRAM

memory, and the Flash Memory Functional Descrip-

tion specifies the symmetrical-sectored Flash architec-

ture and functional commands.

Micron’s 64Mb SyncFlash devices are nonvolatile,

electrically sector-erasable (Flash), programmable

read-only memory containing 67,108,864 bits. Each of

the x16’s 16,777,216-bit banks is organized as 4,096

rows by 256 columns by 16 bits. Each of the x32’s

16,777,216-bit banks is organized as 2,048 rows by 256

columns by 32 bits.

The 64Mb devices are organized into 16 indepen-

dently erasable blocks. To ensure that critical firmware

is protected from accidental erasure or overwrite, the

devices feature sixteen (x32: 128K-Dword; x16: 256K-

word) hardware and software-lockable blocks.

A four-bank architecture supports true concurrent

operations. A read access to any bank can occur simul-

taneously with a background PROGRAM or ERASE op-

eration to any other bank.

SyncFlash memory has a synchronous interface (all

signals are registered on the positive edge of the clock

signal, CLK). Read accesses to the memory are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registra-

tion of an ACTIVE command, followed by a READ com-

mand. The address bits registered coincident with the

ACTIVE command are used to select the bank and row

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

to be accessed. The address bits registered coincident

with the READ command are used to select the starting

column location for the burst access.

The 64Mb devices provide for programmable read

burst lengths of 1, 2, 4, or 8 locations, or the full page,

with a burst terminate option. The x16 device features

an 8-word internal write buffer and the x32 features an

8-Dword internal write buffer that support mode regis-

ter programmed burst write compatibility of 1, 2, 4, or 8

locations.

SyncFlash memory uses an internal pipelined archi-

tecture to achieve high-speed operation.

The 64Mb devices are designed to operate in 3.3V,

low-power memory systems. A deep power-down mode is

provided, along with a power-saving standby mode. All

inputs and outputs are LVTTL-compatible.

SyncFlash memory offers substantial advances in

Flash operating performance, including the ability to

synchronously burst data at a high data rate with auto-

matic column-address generation and the capability

to randomly change column addresses on each clock

cycle during a burst access.

All Flash operations are performed using either a

hardware command sequence (HCS) or a software com-

mand sequence (SCS). HCS operations are used by

memory controllers with native SyncFlash support.

Standard SDRAM controllers can use SCS to perform

Flash operations.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

64Mb: x16, x32 SyncFlash

MT28S4M16B1LC_2.p65 – Rev. 2, Pub. 4/02

3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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