PDM4M4120 データシートの表示（PDF） - Paradigm Technology
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PDM4M4120 Datasheet PDF : 10 Pages
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PRELIMINARY
PDM4M4120
1M x 32 CMOS
Static RAM Module
1
Features
n High-density 4 megabyte Static RAM module
n Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM and Angled SIMM
(Single In-line Memory Module)
n Fast access time: 15ns (max.)
n Surface mounted plastic components on an epoxy
laminate (FR-4) substrate Single 5V (±10%) power
supply
n Multiple VSS pins and decoupling capacitors for
maximum noise immunity
n Inputs/outputs directly TTL compatible
Description
The PDM4M4120 is a 1M x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using eight 1M x 4 static RAMs in plastic SOJ pack-
ages. Availability of four chip select lines (one for
each of two RAMs) provides byte access. The
PDM4M4120 is available with access times as fast as
15ns with minimal power consumption.
The PDM4M4120 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM or
2 Angled SIMM (Single In-line Memory Module). The
ZIP configuration allows 72 pins to be placed on a
package 3.950" long and 0.365" wide. At only 0.590"
high, this low-profile package is ideal for systems
3 with minimum board spacing. The SIMM configura-
tion allows use of edge mounted sockets to secure the
module.
4 All inputs and outputs of the PDM4M4120 are TTL
compatible and operate from a single 5V supply. Full
asynchronous circuitry requires no clock or refresh for
operation and provides equal access and cycle times
for ease of use.
5 Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
6 get system can read the respective levels of PD0, PD1,
PD2, PD3 to determine a 1M depth.
7
Functional Block Diagram
CS1 CS2 CS3 CS4
20
ADDRESS
WE
OE
1M x 32
RAM
4
PD3-PD0
8
8
8
8
I/O31-I/O0
8
9
10
11
12
Rev 2.3
8-51
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