EM78P156EL
OTP ROM
PCRD
P61~P67
PORT
Q
P
R
D
_ CLK
QC
L
PCWR
0M
1
U
X
Q
P
R
D
_ CLK
QC
L
PDWR
PDRD
D
P
R
Q
CLK
C
L
_
Q
IOD
TIN
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7(b) The Circuit of I/O Port and I/O Control Register for P61~P67
IOCE.1
D
P
R
Q
CLK
C
L
_
Q
T10
T11
T17
/SLEP
RE.1
D
P
R
Q
CLK
C
L
_
Q
Interrupt
ENI Instruction
Q
P
R
D
CLK
_
Q
C
L
DISI Instruction
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
Fig. 7(c) Block Diagram of I/O Port 6 with Input Change Interrupt/Wake-up
This specification is subject to change without prior notice.
18
07.29.2004 (V1.3)