EPF011A データシートの表示（PDF） - Unspecified
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EPF011A Datasheet PDF : 124 Pages
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User Guide — EPF011ACD_UG V0.2
2.6.1 Dual Data Pointer (DPTR)
The chip provides dual Data Pointer (DPTR) to facilitate block moves of data. The standard DPTR is a
16-bit register that is used to address Auxiliary Data RAM. With dual DPTR scheme, moving multi bytes
of data from one location to another or moving multi bytes of codes from Program Memory to Data
Memory can be much easier. Of the 2 DPTRs, only one can be selected for any activity which requires
DPTR. A data pointer switch bit (dps) is designed to switch DPTR from one to another. The dps bit is
implemented as a single bit SFR register (bit-0) located at $92. Bit 1~7 in this register is not used.
2.6.2 Accumulator (acc)
Accumulator is used by the CPU to hold operand for most instructions. The mnemonics for accumulator
specific instructions refer to accumulator as A. Accumulator is implemented as an SFR located at $E0.
2.6.3 Program Status Word (psw)
Program Status Word is used by the CPU to report status after most arithmetic operations. 2 bits inside
this register are used to select register banks. Program Status Word is implemented as an SFR located at
$D0.
Table 2-2 psw register
$D0
bit
7
6
5
4
3
2
1
0
R
cy
ac
-
W
rs[1:0]
ov
-
p
Reset:
-
-
-
0
0
-
-
-
cy:
Carry flag.
ac:
Auxiliary Carry flag for BCD operations.
rs[1:0]:
Register bank select.
00 = Bank 0, $00~$07
01 = Bank 1, $08~$0F
10 = Bank 2, $10~$17
11 = Bank 3, $08~$1F
ov:
Overflow flag
p:
Parity flag affected by hardware to indicate odd/even number of "1" bits in the ACC, i.e. even parity.
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