AD7608 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
一致するリスト
AD7608 Datasheet PDF : 32 Pages
| |||
AD7608
Data Sheet
Parameter
t27
t28
t29
Limit at TMIN, TMAX
Min Typ Max
19
24
17
22
24
Unit
ns
ns
ns
ns
ns
Description
Delay from RDE falling edge to FRSTDATA low
A
A
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from 16th SCLK falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25 V
VDRIVE = 2.3 V to 2.7 V
Delay from CSE rising edge until FRSTDATA three-state enabled
A
A
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <40 LSB performance matching between channel sets.
3 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
CONVST A/
CONVST B
CONVST A/
CONVST B
BUSY
CS
RESET
t5
t1
t7
tRESET
tCYCLE
t3
tCONV
t2
t4
Figure 2.CONVST x Timing—Reading After a Conversion
t5
CONVST A/
CONVST B
CONVST A/
CONVST B
tCYCLE
t2
t3
tCONV
t1
BUSY
t6
CS
RESET
t7
tRESET
Figure 3. CONVST x Timing—Reading During a Conversion
CS
RD
DATA:
DB[15:0]
FRSTDATA
t8
t10
t13
INVALID
V1
[17:2]
t26
t24
t11
V1
[1:0]
t14
V2
[17:2]
t27
V2
[1:0]
t15
V8
[17:2]
Figure 4. Parallel Mode Separate CSE and RDE Pulses
A
A
A
A
Rev. A | Page 8 of 32
t9
t16
t17
V8
[1:0]
t29
Share Link: 