TC58DVM72A1FT00 データシートの表示（PDF） - Toshiba

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TC58DVM72A1FT00

128-MBIT (16M u8 BITS/8M x 16BITS) CMOS NAND E²PROM

Toshiba 

TC58DVM72A1FT00/ TC58DVM72F1FT00

TC58DAM72A1FT00/ TC58DAM72F1FT00

Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.

(Refer to Application Note (9) toward the end of this document.)

(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay

is less than 30 ns, RY/BY signal stays Ready.

tCEH t 100 ns

*

*: VIH or VIL

CE

RE

525

526

527 A

A : 0 to 30 ns oBusy signal is not output.

RY/BY

Busy

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta =0° to 70°C, VCC 2.7 V to 3.6 V)

SYMBOL

PARAMETER

MIN

TYP.

tPROG

Programming Time



200

Number of Programming Cycles on Same

N

Page





tBERASE

Block Erasing Time



2

(1): Refer to Application Note (12) toward the end of this document.

MAX

1000

3

10

UNIT

Ps

ms

NOTES

(1)

2003-01-24 6/34

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