MAX3421E データシートの表示（PDF） - Maxim Integrated

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MAX3421E

USB Peripheral/Host Controller with SPI Interface

Maxim Integrated 

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

SS

MISO

SCLK

SPI MODE 0,0 (CPOL = 0, CPHA = 0)

SUSPIRQ URESIRQ SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ IN0BAVIRQ X

MOSI

REG4

REG3

REG2

REG1

REG0

0

DIR

Figure 17. SPI Port in Full-Duplex Mode (Peripheral Mode)

ACKSTAT

SS

SPI MODE 0,0 (CPOL = 0, CPHA = 0)

MISO

HXFRDNIRQ FRAMEIRQ CONNIRQ SUSDNIRQ SNDBAVIRQ RCVDAVIRQ RSMREQIRQ BUSEVENTIRQ X

SCLK

MOSI

REG4

REG3

REG2

REG1

*ACKSTAT BIT NOT USED

Figure 18. SPI Port in Full-Duplex Mode (Host Mode)

1) The SPI master sets the clock to its inactive state.

While SS is high, the master can drive the MOSI pin

to any value.

2) The SPI master selects the MAX3421E by driving

SS low and placing the first data bit (MSB) to write

on the MOSI input.

3) The SPI master turns on its output driver and clocks

the command byte into the MAX3421E on the rising

edges of the SCLK it supplies. The SPI master

changes its MOSI data on the falling edges of SCLK.

4) After eight clock cycles, the master can drive SS

high to deselect the MAX3421E.

REG0

0

DIR

ACKSTAT*

5) To write SPI data, the SPI master keeps its output

driver on and clocks subsequent bytes into the

MOSI pin. To read SPI data, after the eighth clock

cycle the SPI master tri-states its output driver and

begins clocking in data bytes from the MOSI pin.

6) The SPI master terminates the SPI cycle by return-

ing SS high.

Figures 10 and 11 show timing diagrams for full- and

half-duplex operation.

USB Serial-Interface Engine

The serial-interface engine (SIE) does most of the

detailed work required by USB protocol:

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