MAX3421EEHJ データシートの表示（PDF） -

USB Peripheral/Host Controller

with SPI Interface

SS

MISO

SCLK

MODE 0,0

SCLK

MODE 1,1

SPI MODE 0,0 OR 1,1

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

*

MOSI

D7

D6

D5

D4

D3

D2

D1

D0

*

*MSB OF NEXT BYTE IN BURST MODE (SS REMAINS LOW)

Figure 16. SPI Clocking Modes

• INIRQ: When the SEPIRQ bit of the MODE

(R27) register is set high, the BUSACT signal is

removed from the INT output and GPX is used as

an IRQ output pin dedicated to GPIN interrupts if

GPX[B:A] = 10. In this mode, GPIN interrupts

appear only on the GPX pin, and do not appear on

the INT output pin.

• SOF: A square wave with a positive edge that

indicates the USB start-of-frame (Figure 14).

MOSI (Master-Out, Slave-In) and

MISO (Master-In, Slave-Out)

The SPI data pins MOSI and MISO operate differently

depending on the setting of a register bit called FDUPSPI

(full-duplex SPI). Figure 15 shows the two configurations

according to the FDUPSPI bit setting.

In full-duplex mode (FDUPSPI = 1), the MOSI and MISO

pins are separate, and the MISO pin drives only when SS

is low. In this mode, the first eight SCLK edges (after SS =

0) clock the command byte into the MAX3421E on MOSI,

and 8 USB status bits are clocked out of the MAX3421E

on MISO. For an SPI write cycle, any bytes following the

command byte are clocked into the MAX3421E on MOSI,

and zeros are clocked out on MISO. For an SPI read

cycle, any bytes following the command byte are clocked

out of the MAX3421E on MISO and the data on MOSI is

ignored. At the conclusion of the SPI cycle (SS = 1), the

MISO output tri-states.

In half-duplex mode, the MOSI pin is a bidirectional pin

and the MISO pin is tri-stated. This saves a pin in the SPI

interface. Because of the shared data pin, this mode

does not offer the 8 USB status bits (Figures 6 and 7) as

the command byte is clocked into the MAX3421E. The

MISO pin can be left unconnected in half-duplex mode.

SCLK (Serial Clock)

The SPI master provides the MAX3421E SCLK signal to

clock the SPI interface. SCLK has no low-frequency limit,

and can be as high as 26MHz. The MAX3421E changes

its output data (MISO) on the falling edge of SCLK and

samples input data (MOSI) on the rising edge of SCLK.

The MAX3421E ignores SCLK transitions when SS is

high. The inactive level of SCLK may be low or high,

depending on the SPI operating mode (Figure 16).

SS (Slave Select)

The MAX3421E SPI interface is active only when SS is

low. When SS is high, the MAX3421E tri-states the SPI

output pin and resets the internal MAX3421E SPI logic.

If SS goes high before a complete byte is clocked in,

the byte-in-progress is discarded. The SPI master can

terminate an SPI cycle after clocking in the first 8 bits

(the command byte). This feature can be used in a full-

duplex system to retrieve the USB status bits (Figure 6

and 7) without sending or receiving SPI data.

Applications Information

SPI Interface

The MAX3421E operates as an SPI slave device. A reg-

ister access consists of the SPI master first writing an

SPI command byte, followed by reading or writing the

contents of the addressed register (see the Register

Description section for more details). All SPI transfers

are MSB first. The external SPI master provides a clock

signal to the MAX3421E SCLK input. This clock fre-

quency can be between DC and 26MHz. Bit transfers

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