MAX3421E(2006) データシートの表示（PDF） - Maxim Integrated

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MAX3421E
(Rev.:2006)

USB Peripheral/Host Controller with SPI Interface

Maxim Integrated 

(VCC = +3.3V, VL = +3.3V, TA = +25°C.)

USB Peripheral/Host Controller

with SPI Interface

Typical Operating Characteristics

EYE DIAGRAM

4

3

2

1

0

-1

0 10 20 30 40 50 60 70 80

TIME (ns)

Detailed Description

The MAX3421E contains digital logic and analog cir-

cuitry necessary to implement a full-speed USB periph-

eral or a full-/low-speed host compliant to USB

specification rev 2.0. The MAX3421E is selected to

operate as either a host or peripheral by writing to the

HOST bit in the MODE (R27) register. The MAX3421E

features an internal USB transceiver with ±15kV ESD

protection on D+, D-, and VBCOMP. A switchable

1.5kΩ pullup resistor is provided on D+ and switchable

15kΩ pulldown resistors are provided on both D+ and

D-. Any SPI master can communicate with the

MAX3421E through the SPI slave interface that oper-

ates in SPI mode (0,0) or (1,1). An SPI master accesses

the MAX3421E by reading and writing to internal regis-

ters. A typical data transfer consists of writing a first

byte that sets a register address and direction with

additional bytes reading or writing data to the register

or internal FIFO.

In peripheral mode, the MAX3421E contains 384 bytes

of endpoint buffer memory, implementing the following

endpoints:

• EP0: 64-byte bidirectional CONTROL endpoint

• EP1: 2 x 64-byte double-buffered BULK/INT

OUT endpoint

• EP2: 2 x 64-byte double-buffered BULK/INT IN

endpoint

• EP3: 64-byte BULK/INT IN endpoint

The choice to use EP1, EP2, EP3 as BULK or INTER-

RUPT endpoints is strictly a function of the endpoint

descriptors that the SPI master returns to the USB host

during enumeration.

In host mode, the MAX3421E contains 256 bytes of

send and receive FIFO memory:

• SNDFIFO: Send FIFO—double-buffered 64-byte

FIFO

• RCVFIFO: Receive FIFO—double-buffered 64-byte

FIFO

The host FIFOs can send SETUP, BULK, INTERRUPT,

and ISOCHRONOUS requests to a peripheral device, at

full speed or low speed. The MAX3421E accommodates

low-speed devices whether they are directly connected,

or connected through a USB hub. Because the

MAX3421E does much of the host housekeeping, it is

easy to program. The SPI master does a typical host

operation by setting the device address and endpoint,

launching a packet, and waiting for a completion inter-

rupt. Then it examines transfer result bits to determine

how the peripheral responded. It automatically gener-

ates frame markers (full-speed SOF packets or low-

speed keep-alive pulses), and ensures that packets are

dispatched at the correct times relative to these markers.

The MAX3421E register set and SPI interface is optimized

to reduce SPI traffic. An interrupt output pin, INT, notifies

the SPI master when USB service is required; for exam-

ple, when a packet arrives, a packet is sent, or the host

suspends or resumes bus activity. Double-buffered FIFOs

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