MAX11600EKA(2010) データシートの表示（PDF） - Maxim Integrated

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MAX11600EKA
(Rev.:2010)

2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

Maxim Integrated 

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

a) F/S-MODE I2C SERIAL-INTERFACE TIMING

SDA

tSU.DAT

tLOW

tHD.DAT

SCL

tHD.STA

S

tHIGH

tR

tF

b) HS-MODE I2C SERIAL-INTERFACE TIMING

SDA

tSU.DAT

tLOW

tHD.DAT

SCL

tHD.STA

S

tHIGH

tRCL

tFCL

Figure 1. I2C Serial-Interface Timing

tSU.STA

tHD.STA

Sr

A

tSU.STA

tHD.STA

Sr

A

HS MODE

tR

tF t

tBUF

tSU.STO

P

tRDA

S

tFDA

tBUF

tSU.STO

tRCL1

S

F/S MODE

minimize sampling errors with higher source imped-

ances, connect a 100pF capacitor from the analog

input to GND. This input capacitor forms an RC filter

with the source impedance limiting the analog input

bandwidth. For larger source impedances, use a buffer

amplifier to maintain analog input signal integrity.

When operating in internal clock mode, the T/H circuitry

enters its tracking mode on the ninth falling clock edge

of the address byte (see the Slave Address section).

The T/H circuitry enters hold mode two internal clock

cycles later. A conversion or a series of conversions is

then internally clocked (eight clock cycles per conver-

sion) and the MAX11600–MAX11605 hold SCL low.

When operating in external clock mode, the T/H circuit-

ry enters track mode on the seventh falling edge of a

valid slave address byte. Hold mode is then entered on

the falling edge of the eighth clock cycle. The conver-

sion is performed during the next eight clock cycles.

The time required for the T/H circuitry to acquire an

input signal is a function of input capacitance. If the

analog input source impedance is high, the acquisition

time lengthens and more time must be allowed

between conversions. The acquisition time (tACQ) is the

minimum time needed for the signal to be acquired. It is

calculated by:

VDD

IOL = 3mA

SDA

VOUT

400pF

IOH = 0mA

Figure 2. Load Circuit

tACQ ≥ 6.25  (RSOURCE + RIN)  CIN

where RSOURCE is the analog input source impedance,

RIN = 2.5kΩ, and CIN = 18pF. tACQ is 1/fSCL for external

clock mode. For internal clock mode, the acquisition

time is two internal clock cycles. To select RSOURCE,

allow 625ns for tACQ in internal clock mode to account

for clock frequency variations.

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