IDT70P248L データシートの表示（PDF） - Integrated Device Technology

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IDT70P248L

VERY LOW POWER 1.8V 8K/4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70P258/248L

Low Power 1.8V 8K/4K x 16 Dual-Port Static RAM

Pin Names

Left Port

Right Port

Names

CEL

R/WL

CER

R/WR

Chip Enable (Input)

Read/Write Enable (Input)

OEL

A0L - A12L(1)

OER

A0R - A12R(1)

Output Enable (Input)

Address (Input)

I/O0L - I/O15L

I/O0R - I/O15R

Data Input/Output

SEML

SEMR

Semaphore Enable (Input)

UBL

UBR

Upper Byte Select (Input)

LBL

LBR

Lower Byte Select (Input)

INTL

INTR

Interrupt Flag (Output)

BUSYL

BUSYR

Busy Flag

IRR0, IRR1

Input Read Register (Input)

ODR0 - ODR4

Output Drive Register (Output)

SFEN(2)

M/S

Special Function Enable (Input)

Master or Slave Select (Input)

VDD

Power (1.8V) (Input)

VDDQL

Left Port I/O Supply Voltage

(3.0V) (Input)

VSS

Ground (0V) (Input)

5675 tbl 01

Industrial Temperature Range

NOTE:

1. A12X is a NC for IDT70P248.

2. SFEN is active when either CEL = VIL or CER = VIL.

SFEN is inactive when CEL = CER = VIH.

Truth Table I: Non-Contention Read/Write Control

Inputs(1)

Outputs

CE

R/W

OE

UB

LB

SEM

I/O8-15

I/O0-7

Mode

H

X

X

X

X

H

High-Z

High-Z Deselected: Power Down

X

X

X

H

H

H

High-Z

High-Z Both Bytes Deselected

L

L

X

L

H

H

DATAIN

High-Z Write to Upper Byte Only

L

L

X

H

L

H

High-Z

DATAIN Write to Lower Byte Only

L

L

X

L

L

H

DATAIN

DATAIN Write to Both Bytes

L

H

L

L

H

H

DATAOUT

High-Z Read Upper Byte Only

L

H

L

H

L

H

High-Z

DATAOUT Read Lower Byte Only

L

H

L

L

L

H

DATAOUT

DATAOUT Read Both Bytes

X

X

H

X

X

X

High-Z

High-Z Outputs Disabled

NOTE:

1. A0L — A12L ≠ A0R — A12R

6.342

5675 tbl 02

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