UPD4564323 データシートの表示（PDF） - NEC => Renesas Technology

部品番号

コンポーネント説明

一致するリスト

UPD4564323

64M-bit Synchronous DRAM 4-bank, LVTTL

NEC => Renesas Technology 

µPD4564323 for Rev. E

11.3 Write to Read Command Interval

Write command and Read command interval is also 1 cycle.

Only the write data before Read command will be written.

The data bus must be Hi-Z at least one cycle prior to the first DOUT.

Burst length = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

/CAS latency = 2

Command

DQ

Write A Read B

Hi-Z

DA1

QB1

QB2

QB3

QB4

/CAS latency = 3

Command

DQ

Write A Read B

Hi-Z

DA1

QB1

QB2

QB3

QB4

Data Sheet M14376EJ2V0DS00

27

Share Link: