TQ2059 データシートの表示（PDF） - TriQuint Semiconductor
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TQ2059 Datasheet PDF : 6 Pages
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TQ2059
Figure 2. Simplified Block Diagram
Phase
REFCLK
Detector
VCO
÷10
(20 MHz to
35 MHz)
MUX ÷2
MUX
TESTIN
TEST1
TEST2
Control
QN
(200 MHz
to
Q 350 MHz)
Table 1. Mode Selection
Mode
TEST1
TEST2
TESTIN 1
REFCLK 2
1 (Test)
2 (Test)
0
0
0
1
fTESTCLK
“don’t care”
“don't care”
“don't care”
3 (Test)
4 (Bypass)
5 (Normal)
1
0
1
1
1
1
fTESTCLK
0
1
“don't care”
fREFCLK
fREFCLK
Note: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown.
2. REFCLK = 20 MHz to 35 MHz.
3. Q, QN = 200 MHz to 350 MHz.
Q, QN
fTESTCLK ÷ 20
0, 1
fTESTCLK ÷ 2
fREFCLK
10 x fREFCLK 3
Recommended Layout
(Not to scale)
Pin 1 VDD
GND
0.1 µF
GND
REFCLK
(fr(oFmroTmTLToTsLciOllastcoirl)lator)
GND
0.1 µF
VDD
Q 50 OHMS
QN
VDD
0.1 µF
GND
2
For additional information and latest specifications, see our website: www.triquint.com
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